Hao Liang

Orcid: 0000-0002-8097-4707

Affiliations:
  • Hong Kong University of Science and Technology, Department of Electrical and Computer Engineering, Hong Kong


According to our database1, Hao Liang authored at least 19 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
RECom: A Compiler Approach to Accelerating Recommendation Model Inference with Massive Embedding Columns.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2021
Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

2020
Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance Modeling.
ACM Trans. Reconfigurable Technol. Syst., 2020

2019
Ouroboros: An Inference Engine for Deep Learning Based TTS on Embedded Devices.
Proceedings of the 2019 IEEE Hot Chips 31 Symposium (HCS), 2019

PAI-FCNN: FPGA Based CNN Inference System.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

PAI-FCNN: FPGA Based Inference System for Complex CNN Models.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors.
IEEE Trans. Multi Scale Comput. Syst., 2018

Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A Collaborative Framework for FPGA-based CNN Design Modeling and Optimization.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017
A Hybrid Logic Block Architecture in FPGA for Holistic Efficiency.
IEEE Trans. Circuits Syst. II Express Briefs, 2017

HeteroSim: A Heterogeneous CPU-FPGA Simulator.
IEEE Comput. Archit. Lett., 2017

FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates.
Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

2015
Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal Structure.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Hierarchical Library Based Power Estimator for Versatile FPGAs.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015

Hierarchical library based power estimator for versatile FPGAs.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Static hardware task placement on multi-context FPGA using hybrid genetic algorithm.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014
Reconfigurable DSP block design for dynamically reconfigurable architecture.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Hierarchical library-based power estimator for versatile FPGAs (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013
Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013


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