Pallav Gupta

According to our database, Pallav Gupta authored at least 22 papers between 2003 and 2018.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2018

Online Scan Diagnosis : A Novel Approach to Volume Diagnosis.

I-De Huang, Pallav Gupta, Loganathan Lingappan, Vijay Gangaram

Proceedings of the IEEE International Test Conference, 2018

An Effective Methodology for Automated Diagnosis of Functional Pattern Failures to Support Silicon Debug.

Pallav Gupta

Proceedings of the IEEE International Test Conference, 2018

2015

Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal Structure.

Hao Liang, Wei Zhang, Jiale Huang, Shengqi Yang, Pallav Gupta

IEEE Trans. Very Large Scale Integr. Syst., 2015

2013

NBTI-aware circuit node criticality computation.

Shengqi Yang, Wenping Wang, Mark Hagan, Wei Zhang, Pallav Gupta, Yu Cao

ACM J. Emerg. Technol. Comput. Syst., 2013

2012

Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling.

Shengqi Yang, Pallav Gupta, Marilyn Wolf, Dimitrios N. Serpanos, Vijaykrishnan Narayanan, Yuan Xie

ACM Trans. Embed. Comput. Syst., 2012

A physical design tool for carbon nanotube field-effect transistor circuits.

Jiale Huang, Minhao Zhu, Shengqi Yang, Pallav Gupta, Wei Zhang, Steven M. Rubin, Gilda Garretón, Jin He

ACM J. Emerg. Technol. Comput. Syst., 2012

Test generation for clock-domain crossing faults in integrated circuits.

Naghmeh Karimi, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs.

Xiaofang (Maggie) Wang, Pallav Gupta

ACM Trans. Design Autom. Electr. Syst., 2011

Case study: Alleviating hotspots and improving chip reliability via carbon nanotube thermal interface.

Wei Zhang, Jiale Huang, Shengqi Yang, Pallav Gupta

Proceedings of the Design, Automation and Test in Europe, 2011

Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip.

Naghmeh Karimi, Zhiqiu Kong, Krishnendu Chakrabarty, Pallav Gupta, Srinivas Patil

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2008

Automatic Test Generation for Combinational Threshold Logic Networks.

Pallav Gupta, Rui Zhang, Niraj K. Jha

IEEE Trans. Very Large Scale Integr. Syst., 2008

2007

A Test Generation Framework for Quantum Cellular Automata Circuits.

Pallav Gupta, Niraj K. Jha, Loganathan Lingappan

IEEE Trans. Very Large Scale Integr. Syst., 2007

Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies.

Rui Zhang, Pallav Gupta, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006

An Algorithm for Synthesis of Reversible Logic Circuits.

Pallav Gupta, Abhinav Agrawal, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Test generation for combinational quantum cellular automata (QCA) circuits.

Pallav Gupta, Niraj K. Jha, Loganathan Lingappan

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Threshold network synthesis and optimization and its application to nanotechnologies.

Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies.

Rui Zhang, Pallav Gupta, Niraj K. Jha

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Efficient fingerprint-based user authentication for embedded systems.

Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha

Proceedings of the 42nd Design Automation Conference, 2005

2004

An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks.

Pallav Gupta, Rui Zhang, Niraj K. Jha

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies.

Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha

Proceedings of the 2004 Design, 2004

An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology.

Pallav Gupta, Niraj K. Jha

Proceedings of the 2004 Design, 2004

2003

A High-level Interconnect Power Model for Design Space Exploration.

Pallav Gupta, Lin Zhong, Niraj K. Jha

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003