Yijin Guan

Orcid: 0000-0002-8854-2132

According to our database¹, Yijin Guan authored at least 16 papers between 2015 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

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2024

HydraRPC: RPC in the CXL Era.

[BibT_eX]

[DOI]

Proceedings of the 2024 USENIX Annual Technical Conference, 2024

2022

PIMulator-NN: An Event-Driven, Cross-Level Simulation Framework for Processing-In-Memory-Based Neural Network Accelerators.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Flatfish: A Reinforcement Learning Approach for Application-Aware Address Mapping.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network.

[BibT_eX]

[DOI]

IEEE Access, 2022

Accelerating CPU-Based Sparse General Matrix Multiplication With Binary Row Merging.

[BibT_eX]

[DOI]

IEEE Access, 2022

OpSparse: A Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs.

[BibT_eX]

[DOI]

IEEE Access, 2022

184QPS/W 64Mb/mm<sup>2</sup>3D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network.

[BibT_eX]

[DOI]

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Parallel and Distributed Systems, 2022

2021

BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the Advanced Computer Architecture - 13th Conference, 2020

2017

FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

FPGA-based accelerator for long short-term memory recurrent neural networks.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Using Data Compression for Optimizing FPGA-Based Convolutional Neural Network Accelerators.

[BibT_eX]

[DOI]

Proceedings of the Advanced Parallel Processing Technologies, 2017

2015

Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Yijin Guan

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