Yijin Guan

According to our database, Yijin Guan authored at least 15 papers between 2015 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

PIMulator-NN: An Event-Driven, Cross-Level Simulation Framework for Processing-In-Memory-Based Neural Network Accelerators.

Qilin Zheng, Xingchen Li, Yijin Guan, Zongwei Wang, Yimao Cai, Yiran Chen, Guangyu Sun, Ru Huang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Flatfish: A Reinforcement Learning Approach for Application-Aware Address Mapping.

Xingchen Li, Zhihang Yuan, Yijin Guan, Guangyu Sun, Tao Zhang, Rongshan Wei, Dimin Niu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Practical Near-Data-Processing Architecture for Large-Scale Distributed Graph Neural Network.

Linyong Huang, Zhe Zhang, Shuangchen Li, Dimin Niu, Yijin Guan, Hongzhong Zheng, Yuan Xie

IEEE Access, 2022

Accelerating CPU-Based Sparse General Matrix Multiplication With Binary Row Merging.

Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Hongzhong Zheng, Yuan Xie

IEEE Access, 2022

OpSparse: A Highly Optimized Framework for Sparse General Matrix Multiplication on GPUs.

Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Linyong Huang, Hongzhong Zheng, Yuan Xie

IEEE Access, 2022

184QPS/W 64Mb/mm²3D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System.

Dimin Niu, Shuangchen Li, Yuhao Wang, Wei Han, Zhe Zhang, Yijin Guan, Tianchan Guan, Fei Sun, Fei Xue, Lide Duan, Yuanwei Fang, Hongzhong Zheng, Xiping Jiang, Song Wang, Fengguo Zuo, Yubing Wang, Bing Yu, Qiwei Ren, Yuan Xie

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

Hyperscale FPGA-as-a-service architecture for large-scale distributed graph neural network.

Shuangchen Li, Dimin Niu, Yuhao Wang, Wei Han, Zhe Zhang, Tianchan Guan, Yijin Guan, Heng Liu, Linyong Huang, Zhaoyang Du, Fei Xue, Yuanwei Fang, Hongzhong Zheng, Yuan Xie

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

Predicting the Output Structure of Sparse Matrix Multiplication with Sampled Compression Ratio.

Zhaoyang Du, Yijin Guan, Tianchan Guan, Dimin Niu, Nianxiong Tan, Xiaopeng Yu, Hongzhong Zheng, Jianyi Meng, Xiaolang Yan, Yuan Xie

Proceedings of the 28th IEEE International Conference on Parallel and Distributed Systems, 2022

2021

BlockGNN: Towards Efficient GNN Acceleration Using Block-Circulant Weight Matrices.

Zhe Zhou, Bizhao Shi, Zhe Zhang, Yijin Guan, Guangyu Sun, Guojie Luo

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Crane: Mitigating Accelerator Under-utilization Caused by Sparsity Irregularities in CNNs.

Yijin Guan, Guangyu Sun, Zhihang Yuan, Xingchen Li, Ningyi Xu, Shu Chen, Jason Cong, Yuan Xie

IEEE Trans. Computers, 2020

GNN-PIM: A Processing-in-Memory Architecture for Graph Neural Networks.

Zhao Wang, Yijin Guan, Guangyu Sun, Dimin Niu, Yuhao Wang, Hongzhong Zheng, Yinhe Han

Proceedings of the Advanced Computer Architecture - 13th Conference, 2020

2017

FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates.

Yijin Guan, Hao Liang, Ningyi Xu, Wenqiang Wang, Shaoshuai Shi, Xi Chen, Guangyu Sun, Wei Zhang, Jason Cong

Proceedings of the 25th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2017

FPGA-based accelerator for long short-term memory recurrent neural networks.

Yijin Guan, Zhihang Yuan, Guangyu Sun, Jason Cong

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Using Data Compression for Optimizing FPGA-Based Convolutional Neural Network Accelerators.

Yijin Guan, Ningyi Xu, Chen Zhang, Zhihang Yuan, Jason Cong

Proceedings of the Advanced Parallel Processing Technologies, 2017

2015

Optimizing FPGA-based Accelerator Design for Deep Convolutional Neural Networks.

Chen Zhang, Peng Li, Guangyu Sun, Yijin Guan, Bingjun Xiao, Jason Cong

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015