Harrison Liew

Orcid: 0000-0003-3600-3951

According to our database1, Harrison Liew authored at least 14 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Accelerating Hyperdimensional Computing with Vector Machines.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

HDBinaryCore: A 28nm 2048-bit Hyper-Dimensional biosignal classifier achieving 25 nJ/prediction for EMG hand-gesture recognition.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023

Silicon Process Technology Constraints for Standardized Vertical Die-to-Die Interconnects.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
An Adaptable and Scalable Generator of Distributed Massive MIMO Baseband Processing Systems.
J. Signal Process. Syst., 2022

A Highly Energy-Efficient Hyperdimensional Computing Processor for Biosignal Classification.
IEEE Trans. Biomed. Circuits Syst., 2022

Efficient emotion recognition using hyperdimensional computing with combinatorial channel encoding and cellular automata.
Brain Informatics, 2022

Hammer: a modular and reusable physical design flow tool: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
A Scalable Generator for Massive MIMO Baseband Processing Systems with Beamspace Channel Estimation.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2021

A Scalable Massive MIMO Uplink Baseband Processing Generator.
Proceedings of the ICC 2021, 2021

Gemmini: Enabling Systematic Deep-Learning Architecture Evaluation via Full-Stack Integration.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

A Highly Energy-Efficient Hyperdimensional Computing Processor for Wearable Multi-Modal Classification.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021

2020
Chipyard: Integrated Design, Simulation, and Implementation Framework for Custom SoCs.
IEEE Micro, 2020

Invited: Chipyard - An Integrated SoC Research and Implementation Environment.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2017
FPGA with Improved Routability and Robustness in 130nm CMOS with Open-Source CAD Targetability.
CoRR, 2017


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