Randy W. Mann

Orcid: 0000-0001-8373-2052

According to our database1, Randy W. Mann authored at least 18 papers between 1995 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Bias-Dependent Variation in FinFET SRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2020

2019
An Extrinsic Device and Leakage Mechanism in Advanced Bulk FinFET SRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2019

2018
A Retrospective View on the Technology Evolution to Support Low Power Mobile Application.
J. Low Power Electron., 2018

2017
Array Termination Impacts in Advanced SRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Bias-Induced Healing of $V_{\text {min}}$ Failures in Advanced SRAM Arrays.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Soft errors: Reliability challenges in energy-constrained ULP body sensor networks applications.
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

2015
Assessing intrinsic and extrinsic end-of-life risk using functional SRAM wafer level testing.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014
HTOL SRAM Vmin shift considerations in scaled HKMG technologies.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2012
Tracking On-Chip Age Using Distributed, Embedded Sensors.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Nonrandom Device Mismatch Considerations in Nanoscale SRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2012

2011
New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

2010
Limits of bias based assist methods in nano-scale 6T SRAM.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Improving SRAM Vmin and yield by using variation-aware BTI stress.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Sub-threshold Circuit Design with Shrinking CMOS Devices.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2003
Ultralow-power SRAM technology.
IBM J. Res. Dev., 2003

2001
Enchanced multi-threshold (MTCMOS) circuits using variable well bias.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

1995
Silicides and local interconnections for high-performance VLSI applications.
IBM J. Res. Dev., 1995

A half-micron CMOS logic generation.
IBM J. Res. Dev., 1995


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