Farah B. Yahya

According to our database1, Farah B. Yahya authored at least 15 papers between 2011 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
27.1 A 65nm Energy-Harvesting ULP SoC with 256kB Cortex-M0 Enabling an 89.1µW Continuous Machine Health Monitoring Wireless Self-Powered System.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2019
A 1.02 μW Battery-Less, Continuous Sensing and Post-Processing SiP for Wearable Applications.
IEEE Trans. Biomed. Circuits Syst., 2019

Analysis and Design of an Ultra-Low-Power Bluetooth Low-Energy Transmitter With Ring Oscillator-Based ADPLL and 4 $\times$ Frequency Edge Combiner.
IEEE J. Solid State Circuits, 2019

2018
An Ultra-low Power System On Chip Enabling DVS with SR Level Shifting Latches.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Subthreshold SRAM: Challenges, design decisions, and solutions.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A 4.4 nW lossless sensor data compression accelerator for 2.9x system power reduction in wireless body sensors.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Modeling trans-threshold correlations for reducing functional test time in ultra-low power systems.
Proceedings of the IEEE International Test Conference, 2017

FAR: A 4.12μW ferro-electric auto-recovery for battery-less BSN SoCs.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
Improving Reliability and Energy Requirements of Memory in Body Sensor Networks.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

Optimizing SRAM bitcell reliability and energy for IoT applications.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

A 55nm Ultra Low Leakage Deeply Depleted Channel technology optimized for energy minimization in subthreshold SRAM and logic.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
A 6.45 μW Self-Powered SoC With Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios for Portable Biomedical Systems.
IEEE Trans. Biomed. Circuits Syst., 2015

Designing low-VTh STT-RAM for write energy reduction in scaled technologies.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

2011
Determining the minimum energy operating point for embedded SRAM memory.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

A novel technique to measure data retention voltage of large SRAM arrays.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011


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