Hassan Ghasemzadeh Mohammadi

Affiliations:
  • Paderborn University, Department of Computer Science, Germany
  • École Polytechnique Fédérale de Lausanne (EPFL), Integrated Systems Lab (ISL), Switzerland (PhD 2016)
  • Sharif University of Technology, Department of Computer Engineering, Tehran, Iran


According to our database1, Hassan Ghasemzadeh Mohammadi authored at least 15 papers between 2010 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics.
Proceedings of the Machine Learning and Principles and Practice of Knowledge Discovery in Databases, 2021

<i>LDAX</i>: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020
A Hybrid Synthesis Methodology for Approximate Circuits.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

DeepWind: An Accurate Wind Turbine Condition Monitoring Framework via Deep Learning on Embedded Platforms.
Proceedings of the 25th IEEE International Conference on Emerging Technologies and Factory Automation, 2020

2019
Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018
An MCTS-based Framework for Synthesis of Approximate Circuits.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

2016
Robustness Analysis of Controllable-Polarity Silicon Nanowire Devices and Circuits.
PhD thesis, 2016

Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.
ACM J. Emerg. Technol. Comput. Syst., 2016

2015
On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Fault modeling in controllable polarity silicon nanowire circuits.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

2013
Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study.
Proceedings of the 14th Latin American Test Workshop, 2013

A fast TCAD-based methodology for Variation analysis of emerging nano-devices.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2010
Sub-threshold charge recovery circuits.
Proceedings of the 28th International Conference on Computer Design, 2010


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