Hassan Ghasemzadeh Mohammadi
Affiliations:- Paderborn University, Department of Computer Science, Germany
- École Polytechnique Fédérale de Lausanne (EPFL), Integrated Systems Lab (ISL), Switzerland (PhD 2016)
- Sharif University of Technology, Department of Computer Engineering, Tehran, Iran
According to our database1,
Hassan Ghasemzadeh Mohammadi authored at least 22 papers
between 2010 and 2026.
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Bibliography
2026
Sensitivity-Guided Framework for Pruned and Quantized Reservoir Computing Accelerators.
CoRR, March, 2026
Proceedings of the 29th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2026
2025
Design Space Exploration for Approximate Circuits via Checkpointing and DNN-Based Estimators.
IEEE Trans. Very Large Scale Integr. Syst., September, 2025
CRC: Compressed Reservoir Computing on FPGA via Joint HSIC LASSO-based Pruning and Quantization.
WiPiEC Journal, 2025
Swift Synthesis of Approximate Hardware Accelerators Using Generative Adversarial Networks.
Proceedings of the 33rd IFIP/IEEE International Conference on Very Large Scale Integration, 2025
Proceedings of the 55th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2025
2024
DeepApprox: Rapid Deep Learning based Design Space Exploration of Approximate Circuits via Check-pointing.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
2021
FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics.
Proceedings of the Machine Learning and Principles and Practice of Knowledge Discovery in Databases, 2021
<i>LDAX</i>: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
DeepWind: An Accurate Wind Turbine Condition Monitoring Framework via Deep Learning on Embedded Platforms.
Proceedings of the 25th IEEE International Conference on Emerging Technologies and Factory Automation, 2020
2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
2016
PhD thesis, 2016
Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
ACM J. Emerg. Technol. Comput. Syst., 2016
2015
On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014
2013
Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study.
Proceedings of the 14th Latin American Test Workshop, 2013
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
2010
Proceedings of the 28th International Conference on Computer Design, 2010