Ricardo Chaves

Orcid: 0000-0002-4450-3983

According to our database1, Ricardo Chaves authored at least 72 papers between 2003 and 2023.

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Bibliography

2023
Content distribution in a VANET using InterPlanetary file system.
Wirel. Networks, 2023

Security layers and related services within the Horizon Europe NEUROPULS project.
CoRR, 2023

NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS.
CoRR, 2023

Lightweight Network-Based IoT Device Authentication in Cloud Services.
Proceedings of the 31st IEEE International Conference on Network Protocols, 2023


2022
Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher.
IEEE Access, 2022

SmartFusion2 SoC as a security module for the IoT world.
Proceedings of the CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17, 2022

2020
EmuCD: An Emulator for Content Dissemination Protocols in Vehicular Networks.
Future Internet, 2020

When Backscatter Communication Meets Vehicular Networks: Boosting Crosswalk Awareness.
IEEE Access, 2020

Hamming-Code Based Fault Detection Design Methodology for Block Ciphers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Mask Scrambling Against SCA on Reconfigurable TBOX-Based AES.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

TBOX-Based Mask Scrambling Against SCA.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019
Applying Model Checking in the Verification of a Clock Masking Unit.
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

2018
Low-power frequency monitoring circuit for clock failure detection.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

SCA-Resistance for AES: How Cheap Can We Go?
Proceedings of the Progress in Cryptology - AFRICACRYPT 2018, 2018

2017
Cross-domain identity and discovery framework for web calling services.
Ann. des Télécommunications, 2017

Pipelined FPGA coprocessor for elliptic curve cryptography based on residue number system.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

Flexible and low-cost HSM based on non-volatile FPGAs.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

Efficient FPGA Implementation of the SHA-3 Hash Function.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Improving FPGA based SHA-3 structures.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

Area-optimized montgomery multiplication on IGLOO 2 FPGAs.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Decentralized Communications: Trustworthy interoperability in peer-to-peer networks.
Proceedings of the 2017 European Conference on Networks and Communications, 2017

2016
Compact and On-the-Fly Secure Dynamic Reconfiguration for Volatile FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2016

Method for designing two levels RNS reverse converters for large dynamic ranges.
Integr., 2016

Low Power Montgomery Modular Multiplication on Reconfigurable Systems.
IACR Cryptol. ePrint Arch., 2016

Storekeeper: A Security-Enhanced Cloud Storage Aggregation Service.
Proceedings of the 35th IEEE Symposium on Reliable Distributed Systems, 2016

Policy-Based Management for Smart Mobility.
Proceedings of the Intelligent Environments 2016, 2016

2015
Arithmetic-Based Binary-to-RNS Converter Modulo {2<sup>n</sup>±k} for jn-bit Dynamic Range.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Morphable hundred-core heterogeneous architecture for energy-aware computation.
IET Comput. Digit. Tech., 2015

Challenges in designing trustworthy cryptographic co-processors.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Compact dual block AES core on FPGA for CCM Protocol.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

CLEFIA Implementation with Full Key Expansion.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Dual CLEFIA/AES Cipher Core on FPGA.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
An Efficient Scalable RNS Architecture for Large Dynamic Ranges.
J. Signal Process. Syst., 2014

ROM-less RNS-to-binary converter moduli {2<sup>2n</sup> - 1, 2<sup>2n</sup> + 1, 2<sup>n</sup> - 3, 2<sup>n</sup> + 3}.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Method for designing multi-channel RNS architectures to prevent power analysis SCA.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Secure partial dynamic reconfiguration with unsecured external memory.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Accelerating differential power analysis on heterogeneous systems.
Proceedings of the 9th Workshop on Embedded Systems Security, 2014

2013
On the Design of RNS Reverse Converters for the Four-Moduli Set ${\bf\{2^{\mmb n}+1, 2^{\mmb n}-1, 2^{\mmb n}, 2^{{\mmb n}+1}+1\}}$.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Method to Design General RNS Reverse Converters for Extended Moduli Sets.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

RNS Reverse Converters for Moduli Sets With Dynamic Ranges up to (8n+1)-bit.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

HotStream: Efficient Data Streaming of Complex Patterns to Multiple Accelerating Kernels.
Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013

Transparent Application Acceleration by Intelligent Scheduling of Shared Library Calls on Heterogeneous Systems.
Proceedings of the Parallel Processing and Applied Mathematics, 2013

A flexible shared library profiler for early estimation of performance gains in heterogeneous systems.
Proceedings of the International Conference on High Performance Computing & Simulation, 2013

Scalable and high throughput biosensing platform.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A compact and scalable RNS architecture.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
RNS Arithmetic Units for Modulo {2^n+-k}.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Compact CLEFIA Implementation on FPGAS.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

Binary-to-RNS Conversion Units for moduli {2^n ± 3}.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
An improved RNS generator 2<sup>n</sup> +/- k based on threshold logic.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

An improved RNS reverse converter for the {2<sup>2n+1</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>-1} moduli set.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Arithmetic Units for RNS Moduli {2n-3} and {2n+3} Operations.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
Compact and Flexible Microcoded Elliptic Curve Processor for Reconfigurable Devices.
Proceedings of the FCCM 2009, 2009

2008
Cost-Efficient SHA Hardware Accelerators.
IEEE Trans. Very Large Scale Integr. Syst., 2008

Vectorized AES Core for High-throughput Secure Environments.
Proceedings of the High Performance Computing for Computational Science, 2008

BRAM-LUT Tradeoff on a Polymorphic DES Design.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008

Efficient FPGA elliptic curve cryptographic processor over GF(2<sup>m</sup>).
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

On-the-fly attestation of reconfigurable hardware.
Proceedings of the FPL 2008, 2008

Merged Computation for Whirlpool Hashing.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures.
IET Comput. Digit. Tech., 2007

2006
Rescheduling for Optimized SHA-1 Calculation.
Proceedings of the Embedded Computer Systems: Architectures, 2006

Reconfigurable memory based AES co-processor.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Improving SHA-2 Hardware Implementations.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2006

2005
Corrections to "A Universal Architecture for Designing Efficient Modulo 2<sup>n+1</sup> Multipliers".
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

A universal architecture for designing efficient modulo 2<sup>n</sup>+1 multipliers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

2004
{2<sup>n</sup>+1, s<sup>n+k</sup>, s<sup>n</sup>-1}: A New RNS Moduli Set Extension.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

2003
SenToy: an affective sympathetic interface.
Int. J. Hum. Comput. Stud., 2003

Demo: playingfFantasyA with senToy.
Proceedings of the 5th International Conference on Multimodal Interfaces, 2003

Towards tangibility in gameplay: building a tangible affective interface for a computer game.
Proceedings of the 5th International Conference on Multimodal Interfaces, 2003

RDSP: A RISC DSP based on Residue Number System.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

FantasyA and SenToy.
Proceedings of the Extended abstracts of the 2003 Conference on Human Factors in Computing Systems, 2003

SenToy: a tangible interface to control the emotions of a synthetic character.
Proceedings of the Second International Joint Conference on Autonomous Agents & Multiagent Systems, 2003


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