Darshana Jayasinghe

According to our database, Darshana Jayasinghe authored at least 20 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

1LUTSensor: Detecting FPGA Voltage Fluctuations using LookUp Tables.

Darshana Jayasinghe, Brian Udugama, Sri Parameswaran

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

2023

FPGA Based Countermeasures against Side Channel Attacks on Block Ciphers.

Darshana Jayasinghe, Brian Udugama, Sri Parameswaran

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

A Power to Pulse Width Modulation Sensor for Remote Power Analysis Attacks.

Brian Udugama, Darshana Jayasinghe, Hassaan Saadat, Aleksandar Ignjatovic, Sri Parameswaran

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

VITI: A Tiny Self-Calibrating Sensor for Power-Variation Measurement in FPGAs.

Brian Udugama, Darshana Jayasinghe, Hassaan Saadat, Aleksandar Ignjatovic, Sri Parameswaran

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

2021

QuadSeal: Quadruple Balancing to Mitigate Power Analysis Attacks with Variability Effects and Electromagnetic Fault Injection Attacks.

Darshana Jayasinghe, Aleksandar Ignjatovic, Roshan G. Ragel, Jude Angelo Ambrose, Sri Parameswaran

ACM Trans. Design Autom. Electr. Syst., 2021

UCloD: Small Clock Delays to Mitigate Remote Power Analysis Attacks.

Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran

IEEE Access, 2021

2020

LFTSM: Lightweight and Fully Testable SEU Mitigation System for Xilinx Processor-Based SoCs.

Farah Abid, Darshana Jayasinghe, Sompasong Somsavaddy, Sri Parameswaran

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019

SCRIP: Secure Random Clock Execution on Soft Processor Systems to Mitigate Power-based Side Channel Attacks.

Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran

Proceedings of the International Conference on Computer-Aided Design, 2019

RFTC: Runtime Frequency Tuning Countermeasure Using FPGA Dynamic Reconfiguration to Mitigate Power Analysis Attacks.

Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2017

NORA: Algorithmic Balancing without Pre-charge to Thwart Power Analysis Attacks.

Darshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

2016

Template Attacks with Partial Profiles and Dirichlet Priors: Application to Timing Attacks.

Eloi de Chérisey, Sylvain Guilley, Olivier Rioul, Darshana Jayasinghe

Proceedings of the Hardware and Architectural Support for Security and Privacy 2016, 2016

Does it sound as it claims: a detailed side-channel security analysis of QuadSeal countermeasure.

Darshana Jayasinghe, Shivam Bhasin, Sri Parameswaran, Aleksandar Ignjatovic

Proceedings of the ACM International Conference on Computing Frontiers, CF'16, 2016

2015

Side channel attacks in embedded systems: A tale of hostilities and deterrence.

Jude Angelo Ambrose, Roshan G. Ragel, Darshana Jayasinghe, Tuo Li, Sri Parameswaran

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

QuadSeal: Quadruple algorithmic symmetrizing countermeasure against power based side-channel attacks.

Darshana Jayasinghe, Aleksandar Ignjatovic, Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran

Proceedings of the 2015 International Conference on Compilers, 2015

2014

Constant time encryption as a countermeasure against remote cache timing attacks.

Darshana Jayasinghe, Roshan G. Ragel, Dhammika Elkaduwe

CoRR, 2014

Accelerating Correlation Power Analysis Using Graphics Processing Units.

Hasindu Gamaarachchi, Roshan G. Ragel, Darshana Jayasinghe

CoRR, 2014

Countermeasures against Bernstein's remote cache timing attack.

Janaka Alawatugoda, Darshana Jayasinghe, Roshan G. Ragel

CoRR, 2014

Advanced modes in AES: Are they safe from power analysis based side channel attacks?

Darshana Jayasinghe, Roshan G. Ragel, Jude Angelo Ambrose, Aleksandar Ignjatovic, Sri Parameswaran

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

Randomised multi-modulo residue number system architecture for double-and-add to prevent power analysis side channel attacks.

Jude Angelo Ambrose, Héctor Pettenghi, Darshana Jayasinghe, Leonel Sousa

IET Circuits Devices Syst., 2013

2011

A Hardware/Software Countermeasure and a Testing Framework for Cache Based Side Channel Attacks.

Ankita Arora, Sri Parameswaran, Roshan G. Ragel, Darshana Jayasinghe

Proceedings of the IEEE 10th International Conference on Trust, 2011