Elias Vansteenkiste

According to our database1, Elias Vansteenkiste authored at least 22 papers between 2012 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
CRoute: A Fast High-Quality Timing-Driven Connection-Based FPGA Router.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2018
How Preserving Circuit Design Hierarchy During FPGA Packing Leads to Better Performance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Hierarchical Force-Based Block Spreading for Analytical FPGA Placement.
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017
Taming Adversarial Domain Transfer with Structural Constraints for Image Enhancement.
CoRR, 2017

Liquid: High quality scalable placement for large heterogeneous FPGAs.
Proceedings of the International Conference on Field Programmable Technology, 2017

2016
EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures.
Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

A Fully Parameterized Virtual Coarse Grained Reconfigurable Array for High Performance Computing Applications.
Proceedings of the 2016 IEEE International Parallel and Distributed Processing Symposium Workshops, 2016

Runtime-quality tradeoff in partitioning based multithreaded packing.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Liquid: Fast placement prototyping through steepest gradient descent movement.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015
Identification of Dynamic Circuit Specialization Opportunities in RTL Code.
ACM Trans. Reconfigurable Technol. Syst., 2015

FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration.
Microprocess. Microsystems, 2015

Analyzing the divide between FPGA academic and commercial results.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

Estimating circuit delays in FPGAs after technology mapping.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Logic Gates in the routing network of FPGAs (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing.
Proceedings of the 18th IEEE International Conference on Computational Science and Engineering, 2015

2014
TPaR: Place and Route Tools for the Dynamic Reconfiguration of the FPGA's Interconnect Network.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Parameterised FPGA reconfigurations for efficient test set generation.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

2013
A novel tool flow for increased routing configuration similarity in multi-mode circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

A connection-based router for FPGAs.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Efficient implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012
Maximizing the reuse of routing resources in a reconfiguration-aware connection router.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A Connection Router for the Dynamic Reconfiguration of FPGAs.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012


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