Hong-Yan Su

According to our database, Hong-Yan Su authored at least 7 papers between 2011 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map.

Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2019

NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map.

Yih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

MapReduce-based pattern classification for design space analysis.

Yan-Shiun Wu, Hong-Yan Su, Yi-Hsiang Chang, Rasit Onur Topaloglu, Yih-Lang Li

Proceedings of the 2018 International Symposium on VLSI Design, 2018

2017

Pin accessibility evaluating model for improving routability of VLSI designs.

Hong-Yan Su, Shinichi Nishizawa, Yan-Shiun Wu, Jun Shiomi, Yih-Lang Li, Hidetoshi Onodera

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

2015

A Novel Fast Layout Encoding Method for Exact Multilayer Pattern Matching With Prüfer Encoding.

Hong-Yan Su, Chieh-Chu Chen, Yih-Lang Li, An-Chun Tu, Chuh-Jen Wu, Chen-Ming Huang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

SubHunter: a high-performance and scalable sub-circuit recognition method with Prüfer-encoding.

Hong-Yan Su, Chih-Hao Hsu, Yih-Lang Li

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2011

Progressive network-flow based power-aware broadcast addressing for pin-constrained digital microfluidic biochips.

Tsung-Wei Huang, Hong-Yan Su, Tsung-Yi Ho

Proceedings of the 48th Design Automation Conference, 2011