Yih-Lang Li

According to our database1, Yih-Lang Li authored at least 58 papers between 1994 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2020
Smart Shopping Carts Based on Mobile Computing and Deep Learning Cloud Services.
Proceedings of the 2020 IEEE Wireless Communications and Networking Conference, 2020

2019
Incremental Timing-Driven Placement With Approximated Signoff Wire Delay and Regression-Based Cell Delay.
IEEE Trans. Very Large Scale Integr. Syst., 2019

DATC RDF-2019: Towards a Complete Academic Reference Design Flow.
Proceedings of the International Conference on Computer-Aided Design, 2019

NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Fast and Accurate Emissivity and Absolute Temperature Maps Measurement for Integrated Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A Maze Routing-Based Methodology With Bounded Exploration and Path-Assessed Retracing for Constrained Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction.
ACM Trans. Design Autom. Electr. Syst., 2018

DATC RDF: An Open Design Flow from Logic Synthesis to Detailed Routing.
CoRR, 2018

MapReduce-based pattern classification for design space analysis.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

Near-future traffic evaluation based navigation for automated driving vehicles considering traffic uncertainties.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018

DATC RDF: an academic flow from logic synthesis to detailed routing.
Proceedings of the International Conference on Computer-Aided Design, 2018

LESAR: A dynamic line-end spacing aware detailed router.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Pin accessibility evaluating model for improving routability of VLSI designs.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Near-future traffic evaluation based navigation for automated driving vehicles.
Proceedings of the IEEE Intelligent Vehicles Symposium, 2017

DATC RDF: Robust design flow database: Invited paper.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

A Maze Routing-Based Algorithm for ML-OARST with Pre-Selecting and Re-Building Steiner Points.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016
OpenDesign flow database: the infrastructure for VLSI design and design automation research.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Multiple-patterning lithography-aware routing for standard cell layout synthesis.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
A Novel Fast Layout Encoding Method for Exact Multilayer Pattern Matching With Prüfer Encoding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

SubHunter: a high-performance and scalable sub-circuit recognition method with Prüfer-encoding.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Optimizing the Antenna Area and Separators in Layer Assignment of Multilayer Global Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Minimizing Critical Area on Gridless Wire Ordering, Sizing and Spacing.
J. Inf. Sci. Eng., 2014

Skillfully diminishing antenna effect in layer assignment stage.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Density-aware Detailed Placement with Instant Legalization.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Case study for placement solutions in ispd11 and dac12 routability-driven placement contests.
Proceedings of the International Symposium on Physical Design, 2013

Routing congestion estimation with real design constraints.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Optimization of placement solutions for routability.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Optimizing the antenna area and separators in layer assignment of multi-layer global routing.
Proceedings of the International Symposium on Physical Design, 2012

A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

TRIAD: A triple patterning lithography aware detailed router.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Opening: Introduction to CAD contest at ICCAD 2012: CAD contest.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Topology-aware buffer insertion and GPU-based massively parallel rerouting for ECO timing optimization.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
A gridless routing system with nonslicing floorplanning-based crosstalk reduction on gridless track assignment.
ACM Trans. Design Autom. Electr. Syst., 2011

Critical-Trunk-Based Obstacle-Avoiding Rectilinear Steiner Tree Routings and Buffer Insertion for Delay and Slack Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Gridless wire ordering, sizing and spacing with critical area minimization.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

High-quality global routing for multiple dynamic supply voltage designs.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Negotiation-based layer assignment for via count and via overflow minimization.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Multi-threaded collision-aware global routing with bounded-length maze routing.
Proceedings of the 47th Design Automation Conference, 2010

Double patterning lithography aware gridless detailed routing with innovative conflict graph.
Proceedings of the 47th Design Automation Conference, 2010

Minimizing clock latency range in robust clock tree synthesis.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Dead via minimization by simultaneous routing and redundant via insertion.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Critical-trunk based obstacle-avoiding rectilinear steiner tree routings for delay and slack optimization.
Proceedings of the 2009 International Symposium on Physical Design, 2009

Topology-driven cell layout migration with collinear constraints.
Proceedings of the 27th International Conference on Computer Design, 2009

GRPlacer: Improving routability and wire-length of global routing with circuit replacement.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Electronic design automation using a unified optimization framework.
Math. Comput. Simul., 2008

Design optimization of a current mirror amplifier integrated circuit using a computational statistics technique.
Math. Comput. Simul., 2008

Parallel solution of large-scale eigenvalue problem for master equation in protein folding dynamics.
J. Parallel Distributed Comput., 2008

Non-slicing floorplanning-based crosstalk reduction on gridless track assignment for a gridless routing system with fast pseudo-tile extraction.
Proceedings of the 2008 International Symposium on Physical Design, 2008

2007
An Efficient Tile-Based ECO Router Using Routing Graph Reduction and Enhanced Global Routing Flow.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

NEMO: A New Implicit-Connection-Graph-Based Gridless Router With Multilayer Planes and Pseudo Tile Propagation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

A Simulation-Based Hybrid Optimization Technique for Low Noise Amplifier Design Automation.
Proceedings of the Computational Science - ICCS 2007, 7th International Conference, Beijing, China, May 27, 2007

2005
An efficient tile-based ECO router with routing graph reduction and enhanced global routing flow.
Proceedings of the 2005 International Symposium on Physical Design, 2005

1995
Cellular automata for efficient parallel logic and fault simulation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

1994
Logic and Fault Simulation by Cellular Automata.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994


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