Yih-Lang Li
Orcid: 0000-0002-6441-2392
According to our database1,
Yih-Lang Li
authored at least 73 papers
between 1994 and 2024.
Collaborative distances:
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Bibliography
2024
Routability Booster " Synthesize a Routing Friendly Standard Cell Library by Relaxing BEOL Resources.
Proceedings of the 2024 International Symposium on Physical Design, 2024
2023
Skeleton Based Keyframe Detection Framework for Sports Action Analysis: Badminton Smash Case.
IEEE Access, 2023
Periodic Physical Activity Information Segmentation, Counting and Recognition From Video.
IEEE Access, 2023
2022
NCTUcell: A DDA- and Delay-Aware Cell Library Generator for FinFET Structure With Implicitly Adjustable Grid Map.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Spatiotemporal Activity Semantics Understanding Based on Foreground Object Segmentation: iCounter Scenario.
IEEE Access, 2022
Path-Based Pre-Routing Timing Prediction for Modern Very Large-Scale Integration Designs.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022
A Reinforcement Learning Agent for Obstacle-Avoiding Rectilinear Steiner Tree Construction.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022
2021
IPSJ Trans. Syst. LSI Des. Methodol., 2021
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
Proceedings of the 2020 IEEE Wireless Communications and Networking Conference, 2020
MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed Routing.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
/TPlace: Machine Learning-Based Delay-Aware Transistor Placement for Standard Cell Synthesis.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical Design.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the 21st Asia-Pacific Network Operations and Management Symposium, 2020
2019
Incremental Timing-Driven Placement With Approximated Signoff Wire Delay and Regression-Based Cell Delay.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Proceedings of the International Conference on Computer-Aided Design, 2019
NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid Map.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
Fast and Accurate Emissivity and Absolute Temperature Maps Measurement for Integrated Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2018
A Maze Routing-Based Methodology With Bounded Exploration and Path-Assessed Retracing for Constrained Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction.
ACM Trans. Design Autom. Electr. Syst., 2018
Proceedings of the 2018 International Symposium on VLSI Design, 2018
Near-future traffic evaluation based navigation for automated driving vehicles considering traffic uncertainties.
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Proceedings of the IEEE Intelligent Vehicles Symposium, 2017
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017
A Maze Routing-Based Algorithm for ML-OARST with Pre-Selecting and Re-Building Steiner Points.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
2016
OpenDesign flow database: the infrastructure for VLSI design and design automation research.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016
2015
A Novel Fast Layout Encoding Method for Exact Multilayer Pattern Matching With Prüfer Encoding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
SubHunter: a high-performance and scalable sub-circuit recognition method with Prüfer-encoding.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Optimizing the Antenna Area and Separators in Layer Assignment of Multilayer Global Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
J. Inf. Sci. Eng., 2014
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
Case study for placement solutions in ispd11 and dac12 routability-driven placement contests.
Proceedings of the International Symposium on Physical Design, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing.
IEEE Trans. Very Large Scale Integr. Syst., 2012
Optimizing the antenna area and separators in layer assignment of multi-layer global routing.
Proceedings of the International Symposium on Physical Design, 2012
A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Topology-aware buffer insertion and GPU-based massively parallel rerouting for ECO timing optimization.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
A gridless routing system with nonslicing floorplanning-based crosstalk reduction on gridless track assignment.
ACM Trans. Design Autom. Electr. Syst., 2011
Critical-Trunk-Based Obstacle-Avoiding Rectilinear Steiner Tree Routings and Buffer Insertion for Delay and Slack Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Doppler: DPL-aware and OPC-friendly gridless detailed routing with mask density balancing.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
Proceedings of the 47th Design Automation Conference, 2010
Double patterning lithography aware gridless detailed routing with innovative conflict graph.
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Critical-trunk based obstacle-avoiding rectilinear steiner tree routings for delay and slack optimization.
Proceedings of the 2009 International Symposium on Physical Design, 2009
Proceedings of the 27th International Conference on Computer Design, 2009
GRPlacer: Improving routability and wire-length of global routing with circuit replacement.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Math. Comput. Simul., 2008
Design optimization of a current mirror amplifier integrated circuit using a computational statistics technique.
Math. Comput. Simul., 2008
Parallel solution of large-scale eigenvalue problem for master equation in protein folding dynamics.
J. Parallel Distributed Comput., 2008
Non-slicing floorplanning-based crosstalk reduction on gridless track assignment for a gridless routing system with fast pseudo-tile extraction.
Proceedings of the 2008 International Symposium on Physical Design, 2008
2007
An Efficient Tile-Based ECO Router Using Routing Graph Reduction and Enhanced Global Routing Flow.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
NEMO: A New Implicit-Connection-Graph-Based Gridless Router With Multilayer Planes and Pseudo Tile Propagation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
A Simulation-Based Hybrid Optimization Technique for Low Noise Amplifier Design Automation.
Proceedings of the Computational Science - ICCS 2007, 7th International Conference, Beijing, China, May 27, 2007
2005
An efficient tile-based ECO router with routing graph reduction and enhanced global routing flow.
Proceedings of the 2005 International Symposium on Physical Design, 2005
1995
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994