Rasit Onur Topaloglu

Integr., March, 2023

2022

On the Complexity of Generalized Discrete Logarithm Problem.

[BibT_eX]

[DOI]

Cem M. Unsal

CoRR, 2022

Quantum Machine Learning for Material Synthesis and Hardware Security.

[BibT_eX]

[DOI]

CoRR, 2022

Shuttle-Exploiting Attacks and Their Defenses in Trapped-Ion Quantum Computers.

[BibT_eX]

[DOI]

Abdullah Ash-Saki

Swaroop Ghosh

IEEE Access, 2022

Optimization of Quantum Read-Only Memory Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

Quantum Machine Learning for Material Synthesis and Hardware Security (Invited Paper).

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

A Shuttle-Efficient Qubit Mapper for Trapped-Ion Quantum Computers.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Muzzle the Shuttle: Efficient Compilation for Multi-Trap Trapped-Ion Quantum Computers.

[BibT_eX]

[DOI]

Abdullah Ash-Saki

Swaroop Ghosh

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Quantum PUF for Security and Trust in Quantum Computing.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2021

Quantum Generative Models for Small Molecule Drug Discovery.

[BibT_eX]

[DOI]

Junde Li

Swaroop Ghosh

CoRR, 2021

Short Paper: A Quantum Circuit Obfuscation Methodology for Security and Privacy.

[BibT_eX]

[DOI]

Proceedings of the HASP '21: Workshop on Hardware and Architectural Support for Security and Privacy, 2021

Lorax: Machine Learning-Based Oracle Reconstruction With Minimal I/O Patterns.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Split Compilation for Security of Quantum Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Quantum-Classical Hybrid Machine Learning for Image Classification (ICCAD Special Session Paper).

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Sampling-Based Approximate Logic Synthesis: An Explainable Machine Learning Approach.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

A Survey and Tutorial on Security and Resilience of Quantum Computing.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE European Test Symposium, 2021

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Explainable DRC Hotspot Prediction with Random Forest and SHAP Tree Explainer.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2018

Editorial for TODAES Special Issue on Internet of Things System Performance, Reliability, and Security.

[BibT_eX]

[DOI]

Farinaz Koushanfar

ACM Trans. Design Autom. Electr. Syst., 2018

MapReduce-based pattern classification for design space analysis.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on VLSI Design, 2018

2017

Editorial for JETC Special Issue on Alternative Computing Systems.

[BibT_eX]

[DOI]

Naveen Verma

ACM J. Emerg. Technol. Comput. Syst., 2017

2016

ICCAD-2016 CAD contest in pattern classification for integrated circuit design space analysis and benchmark suite.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2014

Guest Editorial Special Section on Optical Interconnects.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

ICCAD-2014 CAD contest in design for manufacturability flow for advanced semiconductor nodes and benchmark suite.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Design and technology co-optimization near single-digit nodes.

[BibT_eX]

[DOI]

Lars W. Liebmann

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013

Chip-scale physical interconnect models (Tutorial).

[BibT_eX]

[DOI]

Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2013

Welcome to ISQED 2013.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

Design with FinFETs: design rules, patterns, and variability.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2012

Efficient pattern relocation for EUV blank defect mitigation.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Block-level 3D IC design with through-silicon-via planning.

[BibT_eX]

[DOI]

Dae Hyun Kim

Sung Kyu Lim

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Device and circuit implications of double-patterning - A designer's perspective.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Fast variational static IR-drop analysis on the graphical processing unit.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

TSV density-driven global placement for 3D stacked ICs.

[BibT_eX]

[DOI]

Dae Hyun Kim

Sung Kyu Lim

Proceedings of the International SoC Design Conference, 2011

GPU programming for EDA with OpenCL.

[BibT_eX]

[DOI]

Benedict R. Gaster

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Self-aligned double patterning decomposition for overlay minimization and hot spot detection.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

Applications driving 3D integration and corresponding manufacturing challenges.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

2010

3-2-1 contact: an experimental approach to the analysisof contacts in 45 nm and below.

[BibT_eX]

[DOI]

Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

Assessing chip-level impact of double patterning lithography.

[BibT_eX]

[DOI]

Kwangok Jeong

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009

Is overlay error more important than interconnect variations in double patterning?

[BibT_eX]

[DOI]

Kwangok Jeong

Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008

Characterization, modeling and optimization of fills and stress in semiconductor integrated circuits.

[BibT_eX]

[DOI]

PhD thesis, 2008

Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion.

[BibT_eX]

[DOI]

Puneet Sharma

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Process Variation Characterization and Modeling of Nanoparticle Interconnects for Foldable Electronics.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007

Process Variation-Aware Multiple-Fault Diagnosis of Thermometer-Coded Current-Steering DACs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Energy-Minimization Model for Fill Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A DOE Set for Normalization-Based Extraction of Fill Impact on Capacitances.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Exploiting STI stress for performance.

[BibT_eX]

[DOI]

Puneet Sharma

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Standard Cell and Custom Circuit Optimization using Dummy Diffusions through STI Width Stress Effect Utilization.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Early, Accurate and Fast Yield Estimation through Monte Carlo-Alternative Probabilistic Behavioral Analog System Simulations.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Generation of design guarantees for interconnect matching.

[BibT_eX]

[DOI]

Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Monte Carlo-Alternative Probabilistic Simulations for Analog Systems.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

2005

A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs.

[BibT_eX]

[DOI]

Alex Orailoglu

Proceedings of the 42nd Design Automation Conference, 2005

Forward discrete probability propagation method for device performance characterization under process variations.

[BibT_eX]

[DOI]

Alex Orailoglu

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

On mismatch in the deep sub-micron era - from physics to circuits.

[BibT_eX]

[DOI]