Jun Shiomi
According to our database1,
Jun Shiomi
authored at least 47 papers
between 2015 and 2024.
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Bibliography
2024
Edge-Oriented Point Cloud Compression by Moving Object Detection for Realtime Smart Monitoring.
Proceedings of the 21st IEEE Consumer Communications & Networking Conference, 2024
2023
Nonvolatile Storage Cells Using FiCC for IoT Processors with Intermittent Operations.
IEICE Trans. Electron., October, 2023
Approximation-Based System Implementation for Real-Time Minimum Energy Point Tracking over a Wide Operating Performance Region.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., March, 2023
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
DependableHD: A Hyperdimensional Learning Framework for Edge-Oriented Voltage-Scaled Circuits.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023
2022
A Hardware Efficient Reservoir Computing System Using Cellular Automata and Ensemble Bloom Filter.
IEICE Trans. Inf. Syst., 2022
Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022
Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022
Proceedings of the 2022 IEEE/IFIP Network Operations and Management Symposium, 2022
Approximation-Based Implementation for a Minimum Energy Point Tracking Algorithm over a Wide Operating Performance Region.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
Zero-standby-power Nonvolatile Standard Cell Memory Using FiCC for IoT Processors with Intermittent Operations.
Proceedings of the IEEE Symposium in Low-Power and High-Speed Chips, 2022
DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
MOSDA: On-Chip Memory Optimized Sparse Deep Neural Network Accelerator With Efficient Index Matching.
IEEE Open J. Circuits Syst., 2021
A DLL-Based Body Bias Generator with Independent P-Well and N-Well Biasing for Minimum Energy Operation.
IEICE Trans. Electron., 2021
Evaluation Metrics for the Cost of Data Movement in Deep Neural Network Acceleration.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
Supply and Threshold Voltage Scaling for Minimum Energy Operation over a Wide Operating Performance Region.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021
2020
Dynamic Supply and Threshold Voltage Scaling towards Runtime Energy Optimization over a Wide Operating Performance Region.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020
A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
Proceedings of the International Conference on Rebooting Computing, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
A DLL-based Body Bias Generator for Minimum Energy Operation with Independent P-well and N-well Bias.
Proceedings of the 2020 IEEE Asia Pacific Conference on Circuits and Systems, 2020
2019
Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing.
Integr., 2019
On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
IEICE Trans. Electron., 2019
An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator.
Proceedings of the 2019 IEEE/ACM Workshop on Photonics-Optics Technology Oriented Networking, 2019
BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
J. Low Power Electron., 2018
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018
An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018
2017
Performance Modeling and On-Chip Memory Structures for Minimum Energy Operation in Voltage-Scaled LSI Circuits.
PhD thesis, 2017
A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
2016
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016
Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016
A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring.
IEEE J. Solid State Circuits, 2015
Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
An energy-efficient on-chip memory structure for variability-aware near-threshold operation.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Microarchitectural-level statistical timing models for near-threshold circuit design.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015