Jun Shiomi

According to our database1, Jun Shiomi authored at least 22 papers between 2015 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2020
A Synthesis Method for Power-Efficient Integrated Optical Logic Circuits Towards Light Speed Processing.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

On-chip Memory Optimized CNN Accelerator with Efficient Partial-sum Accumulation.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019
Area-efficient fully digital memory using minimum height standard cells for near-threshold voltage computing.
Integr., 2019

On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

A Design Method of a Cell-Based Amplifier for Body Bias Generation.
IEICE Trans. Electron., 2019

An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator.
Proceedings of the 2019 IEEE/ACM Workshop on Photonics-Optics Technology Oriented Networking, 2019

BDD-based synthesis of optical logic circuits exploiting wavelength division multiplexing.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Minimum Energy Point Tracking with All-Digital On-Chip Sensors.
J. Low Power Electron., 2018

Maximizing Energy Efficiency of on-Chip Caches Exploiting Hybrid Memory Structure.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing.
Proceedings of the 2018 IEEE International Conference on Rebooting Computing, 2018

2017
A Necessary and Sufficient Condition of Supply and Threshold Voltages in CMOS Circuits for Minimum Energy Point Operation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

Pin accessibility evaluating model for improving routability of VLSI designs.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

2016
Analytical Stability Modeling for CMOS Latches in Low Voltage Operation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

Fully digital on-chip memory using minimum height standard cells for near-threshold voltage computing.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Variability- and correlation-aware logical effort for near-threshold circuit design.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

A closed-form stability model for cross-coupled inverters operating in sub-threshold voltage region.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring.
IEEE J. Solid State Circuits, 2015

Statistical Timing Modeling Based on a Lognormal Distribution Model for Near-Threshold Circuit Optimization.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

An energy-efficient on-chip memory structure for variability-aware near-threshold operation.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Microarchitectural-level statistical timing models for near-threshold circuit design.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015


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