Hong Zhang
Orcid: 0000-0003-2746-1846Affiliations:
- Xi'an Jiaotong University, School of Microelectronics, China (PhD 2008)
According to our database1,
Hong Zhang
authored at least 37 papers
between 2011 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
A 10-kHz BW 104.3-dB DR discrete-time delta-sigma modulator with ring-amplifier-based integrator.
Microelectron. J., February, 2024
A 2-2 MASH ΔΣ ADC with fast-charge CLS input buffer and dual double sampling achieving 103.3-dB SNDR and ±2.5-ppm/FSR INL.
Microelectron. J., February, 2024
2023
A 1.25-MHz-BW, 83-dB SNDR Pipelined Noise-Shaping SAR ADC With MASH 2-2 Structure and kT/C Noise Cancellation.
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
An 84dB-SNDR 1-0 Quasi-MASH NS SAR with LSB Repeating and 12-bit Bridge-Crossing Segmented CDAC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
A 2.5-MHz BW, 75-dB SNDR Noise-Shaping SAR ADC With a 1st-Order Hybrid EF-CIFF Structure Assisted by Unity-Gain Buffer.
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 6-GHz Bandwidth Input Buffer Based on AC-Coupled Flipped Source Follower for 12-bit 8-GS/s ADC in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 1-V 2.69-ppm/°C 0.8-μW bandgap reference with piecewise exponential curvature compensation.
Microelectron. J., 2022
Estimation of Broadband Time-Interleaved ADC's Impairments and Performance Using Only Single-Tone Measurements.
IEEE Access, 2022
2021
A Closed-Loop Neuromodulation Chipset With 2-Level Classification Achieving 1.5-Vpp CM Interference Tolerance, 35-dB Stimulation Artifact Rejection in 0.5ms and 97.8%-Sensitivity Seizure Detection.
IEEE Trans. Biomed. Circuits Syst., 2021
Linearity Boosting Technique with Adaptive Sampling Switch Assisted by Signal Prediction for Multi-Channel ADCs in Standard CMOS Process.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021
2020
A 48 pW, 0.34 V, 0.019%/V Line Sensitivity Self-Biased Subthreshold Voltage Reference With DIBL Effect Compensation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
Sparsity Constrained Recursive Generalized Maximum Correntropy Criterion With Variable Center Algorithm.
IEEE Trans. Circuits Syst., 2020
A Configurable Noise-Shaping Band-Pass SAR ADC With Two-Stage Clock-Controlled Amplifier.
IEEE Trans. Circuits Syst., 2020
A +0.66/-0.73 °C Inaccuracy, 1.99-μW Time-Domain CMOS Temperature Sensor With Second-Order ΔΣ Modulator and On-Chip Reference Clock.
IEEE Trans. Circuits Syst., 2020
An integrated low-power Binary-PAM based wireless telemetry circuit for implantable cardiac pacemakers.
Microelectron. J., 2020
26.3 A Closed-Loop Neuromodulation Chipset with 2-Level Classification Achieving 1.5Vpp CM Interference Tolerance, 35dB Stimulation Artifact Rejection in 0.5ms and 97.8% Sensitivity Seizure Detection.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
A 12-Cell Battery Monitor IC with 2-Channel 16-bit ADCs and Isolated Bidirectional Data Interface.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
Low-Voltage High-Linearity Differential Input Buffer with CurrentAmplifier Feed-Forward Compensation for High-Speed ADCs.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
2019
A 10-Bit 200-kS/s 1.76- $\mu$ W SAR ADC With Hybrid CAP-MOS DAC for Energy-Limited Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Joint background calibration of gain and timing mismatch errors with low hardware cost for time-interleaved ADCs.
IET Circuits Devices Syst., 2019
A Pseudo-Constant Frequency Constant On-Time Buck Converter With Internal Current Ripple Injection and Output DC Offset Cancellation.
IEEE Access, 2019
Proceedings of the 2019 IEEE/CVF International Conference on Computer Vision, 2019
2018
A Low-Power Pipelined-SAR ADC Using Boosted Bucket-Brigade Device for Residue Charge Processing.
IEEE Trans. Very Large Scale Integr. Syst., 2018
A 0.6-V 10-bit 200-kS/s SAR ADC With Higher Side-Reset-and-Set Switching Scheme and Hybrid CAP-MOS DAC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEEE Trans. Biomed. Circuits Syst., 2018
A 10-bit 200-kS/s 1.76-μW SAR ADC with Hybrid CAP-MOS DAC for Energy-Limited Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
A 1-V 3.1-ppm/°C 0.8-μW Bandgap Reference with Piecewise Exponential Curvature Compensation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
All-Digital Calibration of Timing Mismatch Error in Time-Interleaved Analog-to-Digital Converters.
IEEE Trans. Very Large Scale Integr. Syst., 2017
A low energy ASIC for triple-chamber cardiac pacemakers with contact resistance measurement.
Microelectron. J., 2017
2016
Proceedings of the 12th International Conference on Computational Intelligence and Security, 2016
2015
A multi-cell battery pack monitoring chip based on 0.35-µm BCD technology for electric vehicles.
IEICE Electron. Express, 2015
A mixed-signal ASIC for triple-chamber cardiac pacemakers with heart resistance measurement.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
An inductive wireless telemetry circuit with OOK modulation for implantable cardiac pacemakers.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011