Huiying Lan

Orcid: 0000-0003-3120-5773

According to our database1, Huiying Lan authored at least 18 papers between 2016 and 2026.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

Online presence:

On csauthors.net:

Bibliography

2026
HighP: In-Memory Acceleration of SpGEMM With High Bank-Level Parallelism.
IEEE Trans. Computers, January, 2026

A Data-Driven Dynamic Execution Orchestration Architecture.
Proceedings of the 31st ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2026

2025
Para-Pipe: Exploiting Hierarchical Operator Parallelism of ML Computational Graphs on SoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2025

TL: Automatic End-to-End Compiler of Tile-Based Languages for Spatial Dataflow Architectures.
CoRR, December, 2025

Efficient Partitioning Vision Transformer on Edge Devices for Distributed Inference.
Proceedings of the 45th IEEE International Conference on Distributed Computing Systems, 2025

High Performance Computing Framework for Secure Variable Selection on Genome-Wide Association Studies with Adaptive Vertical Federated Learning.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2025

Efficient Partitioning Deep Learning Models for Medical Image Analysis on Iot Devices.
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2025

2024
ED-ViT: Splitting Vision Transformer for Distributed Inference on Edge Devices.
CoRR, 2024

FusionFrame: A Fusion Dataflow Scheduling Framework for DNN Accelerators via Analytical Modeling.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2024

2021
Review on Fuzz Testing for Protocols in Industrial Control Systems.
Proceedings of the Sixth IEEE International Conference on Data Science in Cyberspace, 2021

2019
Addressing Sparsity in Deep Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

2018
An Instruction Set Architecture for Machine Learning.
ACM Trans. Comput. Syst., 2018

BenchIP: Benchmarking Intelligence Processors.
J. Comput. Sci. Technol., 2018

Leveraging Subgraph Extraction for Performance Portable Programming Frameworks on DL Accelerators.
Proceedings of the Network and Parallel Computing, 2018

DLIR: An Intermediate Representation for Deep Learning Processors.
Proceedings of the Network and Parallel Computing, 2018

2017
DLPlib: A Library for Deep Learning Processor.
J. Comput. Sci. Technol., 2017

BENCHIP: Benchmarking Intelligence Processors.
CoRR, 2017

2016
Cambricon-X: An accelerator for sparse neural networks.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016


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