Hyeonchan Lim

According to our database, Hyeonchan Lim authored at least 15 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Reconfigurable Multi-Bit Scan Flip-Flop for Cell-Aware Diagnosis.

Hyeonchan Lim, Tae-Hyun Kim, Sungho Kang

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

2022

Scan Cell Modification for Intra Cell-Aware Scan Chain Diagnosis.

Hyeonchan Lim, Hyojoon Yun, Sungho Kang

IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Hybrid Test Scheme for Automotive IC in Multisite Testing.

Hyeonchan Lim, Hyojoon Yun, Sungho Kang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Cell-Aware Scan Diagnosis Using Partially Synchronous Set and Reset.

Hyeonchan Lim, Hyojoon Yun, Juyong Lee, Sungho Kang

Proceedings of the 19th International SoC Design Conference, 2022

Logic Diagnosis Based on Deep Learning for Multiple Faults.

Tae Hyun Kim, Hyeonchan Lim, Minho Cheong, Hyojoon Yun, Sungho Kang

Proceedings of the 19th International SoC Design Conference, 2022

2021

Enhanced Postbond Test Architecture for Bridge Defects Between the TSVs.

Jungil Mok, Hyeonchan Lim, Sungho Kang

IEEE Trans. Very Large Scale Integr. Syst., 2021

2020

Robust Secure Shield Architecture for Detection and Protection Against Invasive Attacks.

Young-Woo Lee, Hyeonchan Lim, Youngkwang Lee, Sungho Kang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Diagnosis of Scan Chain Faults Based-on Machine-Learning.

Hyeonchan Lim, Tae Hyun Kim, Seunghwan Kim, Sungho Kang

Proceedings of the International SoC Design Conference, 2020

2018

A Software-based Scan Chain Diagnosis for Double Faults in A Scan Chain.

Hyeonchan Lim, Seokjun Jang, Sungho Kang

Proceedings of the International SoC Design Conference, 2018

2017

Grouping-Based TSV Test Architecture for Resistive Open and Bridge Defects in 3-D-ICs.

Young-Woo Lee, Hyeonchan Lim, Sungho Kang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Off-chip test architecture for improving multi-site testing efficiency using tri-state decoder and 3V-level encoder.

Sungyoul Seo, Hyeonchan Lim, Soyeon Kang, Sungho Kang

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Broadcast scan compression based on deterministic pattern generation algorithm.

Hyeonchan Lim, Sungyoul Seo, Soyeon Kang, Sungho Kang

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Test data reduction method based on berlekamp-massey algorithm.

Hyeonchan Lim, Junghwan Kim, Soyeon Kang, Sungho Kang

Proceedings of the International SoC Design Conference, 2017

2016

Software-based embedded core test using multi-polynomial for test data reduction.

Soyeon Kang, Inhyuk Choi, Hyeonchan Lim, Sungyoul Seo, Sungho Kang

Proceedings of the International SoC Design Conference, 2016

2015

Scan Chain Reordering-Aware X-Filling and Stitching for Scan Shift Power Reduction.

Sungyoul Seo, Yong Lee, Hyeonchan Lim, Joohwan Lee, Hongbom Yoo, Yojoung Kim, Sungho Kang

Proceedings of the 24th IEEE Asian Test Symposium, 2015