Jungil Mok

According to our database, Jungil Mok authored at least 3 papers between 2021 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

A 16-Gb 37-Gb/s GDDR7 DRAM With PAM3-Optimized TRX Equalization and ZQ Calibration.

Sung-Yong Cho, Moon-Chul Choi, Jaehyeok Baek, Donggun An, Sang-Hoon Kim, Daewoong Lee, Seongyeal Yang, Se-Mi Kim, Gil-Young Kang, Juseop Park, Kyung-Ho Lee, Hwan-Chul Jung, Gun-hee Cho, Chan-Yong Lee, Hye-Ran Kim, Yong-Jae Shin, Hanna Park, Sang-Yong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim, Unhak Lim, Hongjun Jin, YoungSeok Lee, Young-Tae Kim, Heonjoo Ha, Jinchan Ahn, Wonju Sung, Yoontaek Jang, Hoyoung Song, Hyodong Ban, TaeHoon Park, Changsik Yoo, Tae-Young Oh, SangJoon Hwang

IEEE J. Solid State Circuits, January, 2025

2024

13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration.

Sung-Yong Cho, Moon-Chul Choi, Jaehyeok Baek, Donggun An, Sanghoon Kim, Daewoong Lee, Seongyeal Yang, Gil-Young Kang, Juseop Park, Kyungho Lee, Hwan-Chul Jung, Gun-hee Cho, Chanyong Lee, Hye-Ran Kim, Yong-Jae Shin, Hanna Park, Sangyong Lee, Jonghyuk Kim, Bokyeon Won, Jungil Mok, Kijin Kim, Unhak Lim, Hongjun Jin, YoungSeok Lee, Young-Tae Kim, Heonjoo Ha, Jinchan Ahn, Wonju Sung, Yoontaek Jang, Hoyoung Song, Hyodong Ban, TaeHoon Park, Tae-Young Oh, Changsik Yoo, SangJoon Hwang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2021

Enhanced Postbond Test Architecture for Bridge Defects Between the TSVs.

Jungil Mok, Hyeonchan Lim, Sungho Kang

IEEE Trans. Very Large Scale Integr. Syst., 2021