Hyokeun Lee

Orcid: 0000-0002-0824-6238

According to our database1, Hyokeun Lee authored at least 14 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Salus: Efficient Security Support for CXL-Expanded GPU Memory.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023
An In-Module Disturbance Barrier for Mitigating Write Disturbance in Phase-Change Memory.
IEEE Trans. Computers, April, 2023

CryptoMMU: Enabling Scalable and Secure Access Control of Third-Party Accelerators.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

A Spatio-Temporal Switchable Data Prefetcher for Convolutional Neural Networks.
Proceedings of the 20th International SoC Design Conference, 2023

ERAS: A Flexible and Scalable Framework for Seamless Integration of RTL Models with Structural Simulation Toolkit.
Proceedings of the IEEE International Symposium on Workload Characterization, 2023

Characterizing Memory Access Patterns of Various Convolutional Neural Networks for Utilizing Processing-in-Memory.
Proceedings of the International Conference on Electronics, Information, and Communication, 2023

SDM: Sharing-Enabled Disaggregated Memory System with Cache Coherent Compute Express Link.
Proceedings of the 32nd International Conference on Parallel Architectures and Compilation Techniques, 2023

2022
WL-WD: Wear-Leveling Solution to Mitigate Write Disturbance Errors for Phase-Change Memory.
IEEE Access, 2022

PCMCsim: An Accurate Phase-Change Memory Controller Simulator and its Performance Analysis.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

Performance Analysis of a Phase-Change Memory System on Various CNN Inference Workloads.
Proceedings of the 19th International SoC Design Conference, 2022

2020
A Low-Cost and High-Throughput FPGA Implementation of the Retinex Algorithm for Real-Time Video Enhancement.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Mitigating Write Disturbance Errors of Phase-Change Memory as In-Module Approach.
CoRR, 2020

2019
Integration and Boost of a Read-Modify-Write Module in Phase Change Memory System.
IEEE Trans. Computers, 2019

HAD-TWL: Hot Address Detection-Based Wear Leveling for Phase-Change Memory Systems with Low Latency.
IEEE Comput. Archit. Lett., 2019


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