Arun Rodrigues

According to our database1, Arun Rodrigues
  • authored at least 43 papers between 2000 and 2017.
  • has a "Dijkstra number"2 of four.

Timeline

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Bibliography

2017
Optical interconnects for extreme scale computing systems.
Parallel Computing, 2017

Two-level main memory co-design: Multi-threaded algorithmic primitives, analysis, and simulation.
J. Parallel Distrib. Comput., 2017

Performance analysis for using non-volatile memory DIMMs: opportunities and challenges.
Proceedings of the International Symposium on Memory Systems, 2017

2016
Analyzing allocation behavior for multi-level memory.
Proceedings of the Second International Symposium on Memory Systems, 2016

Low Latency, High Bisection-Bandwidth Networks for Exascale Memory Systems.
Proceedings of the Second International Symposium on Memory Systems, 2016

Multi-Level Memory Policies: What You Add Is More Important Than What You Take Out.
Proceedings of the Second International Symposium on Memory Systems, 2016

End-to-End Modeling and Optimization of Power Consumption in HPC Interconnects.
Proceedings of the 45th International Conference on Parallel Processing Workshops, 2016

2015
Design Methodology for Optimizing Optical Interconnection Networks in High Performance Systems.
Proceedings of the High Performance Computing - 30th International Conference, 2015

Understanding Energy Aspects of Processing-near-Memory for HPC Workloads.
Proceedings of the 2015 International Symposium on Memory Systems, 2015

The Potential and Perils of Multi-Level Memory.
Proceedings of the 2015 International Symposium on Memory Systems, 2015

Two-Level Main Memory Co-Design: Multi-threaded Algorithmic Primitives, Analysis, and Simulation.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium, 2015

2014
Exascale design space exploration and co-design.
Future Generation Comp. Syst., 2014

Using a complementary emulation-simulation co-design approach to assess application readiness for processing-in-memory systems.
Proceedings of the 1st International Workshop on Hardware-Software Co-Design for High Performance Computing, 2014

Abstract machine models and proxy architectures for exascale computing.
Proceedings of the 1st International Workshop on Hardware-Software Co-Design for High Performance Computing, 2014

2012
SST: A Scalable Parallel Framework for Architecture-Level Performance, Power, Area and Thermal Simulation.
Comput. J., 2012

Instruction-based energy estimation methodology for asymmetric manycore processor simulations.
Proceedings of the International ICST Conference on Simulation Tools and Techniques, 2012

Improvements to the structural simulation toolkit.
Proceedings of the International ICST Conference on Simulation Tools and Techniques, 2012

SST + gem5 = a scalable simulation infrastructure for high performance computing.
Proceedings of the International ICST Conference on Simulation Tools and Techniques, 2012

A universal parallel front-end for execution driven microarchitecture simulation.
Proceedings of the 2012 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, 2012

2011
The structural simulation toolkit.
SIGMETRICS Performance Evaluation Review, 2011

A framework for architecture-level power, area, and thermal simulation and its application to network-on-chip design exploration.
SIGMETRICS Performance Evaluation Review, 2011

System implications of memory reliability in exascale computing.
Proceedings of the Conference on High Performance Computing Networking, 2011

Achieving Exascale Computing through Hardware/Software Co-design.
Proceedings of the Recent Advances in the Message Passing Interface, 2011

Let there be light!: the future of memory systems is photonics and 3D stacking.
Proceedings of the 2011 ACM SIGPLAN workshop on Memory Systems Performance and Correctness: held in conjunction with PLDI '11, 2011

Simulating Application Resilience at Exascale.
Proceedings of the Euro-Par 2011: Parallel Processing Workshops - CCPI, CGWS, HeteroPar, HiBB, HPCVirt, HPPC, HPSS, MDGS, ProPer, Resilience, UCHPC, VHPC, Bordeaux, France, August 29, 2011

2010
On the Path to Exascale.
IJDST, 2010

Embedded Systems and Exascale Computing.
Computing in Science and Engineering, 2010

Exascale Computing and the Role of Co-Design.
Proceedings of the High Performance Computing: From Grids and Clouds to Exascale, 2010

2007
Evaluating synchronization techniques for light-weight multithreaded/multicore architectures.
Proceedings of the SPAA 2007: Proceedings of the 19th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2007

Simulating Red Storm: Challenges and Successes in Building a System Simulation.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

An architecture to perform NIC based MPI matching.
Proceedings of the 2007 IEEE International Conference on Cluster Computing, 2007

2006
Implications of application usage characteristics for collective communication offload.
IJHPCN, 2006

Poster reception - The structural simulation toolkit: exploring novel architectures.
Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, 2006

Scientific applications vs. SPEC-FP: a comparison of program behavior.
Proceedings of the 20th Annual International Conference on Supercomputing, 2006

Fine-Grained Message Pipelining for Improved MPI Performance.
Proceedings of the 2006 IEEE International Conference on Cluster Computing, 2006

2005
A Hardware Acceleration Unit for MPI Queue Processing.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Enhancing NIC Performance for MPI using Processing-in-Memory.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

The implications of working set analysis on supercomputing memory hierarchy design.
Proceedings of the 19th Annual International Conference on Supercomputing, 2005

Accelerating List Management for MPI.
Proceedings of the 2005 IEEE International Conference on Cluster Computing (CLUSTER 2005), September 26, 2005

2004
Characterizing a new class of threads in scientific applications for high end supercomputers.
Proceedings of the 18th Annual International Conference on Supercomputing, 2004

2003
Bouncing Threads: Merging a New Execution Model into a Nanotechnology Memory.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Implications of a PIM Architectural Model for MPI.
Proceedings of the 2003 IEEE International Conference on Cluster Computing (CLUSTER 2003), 2003

2000
The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems.
Proceedings of the Intelligent Memory Systems, Second International Workshop, 2000


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