Abhishek Bhattacharjee

Orcid: 0000-0003-2742-2679

Affiliations:
  • Yale University, Computer Systems Lab, New Haven, CT, USA
  • Rutgers University, Department of Computer Science, Piscataway, NJ, USA
  • Princeton University, NJ, USA


According to our database1, Abhishek Bhattacharjee authored at least 72 papers between 2008 and 2023.

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Bibliography

2023
Design and Lifetime Estimation of Low-Power 6-Input Look-Up Table Used in Modern FPGA.
J. Circuits Syst. Comput., May, 2023

HALO: A Hardware-Software Co-Designed Processor for Brain-Computer Interfaces.
IEEE Micro, 2023

Quantum Cognitive Modeling: New Applications and Systems Research Directions.
CoRR, 2023

Mitigating Catastrophic Forgetting in Long Short-Term Memory Networks.
CoRR, 2023

A Multi-Site Accelerator-Rich Processing Fabric for Scalable Brain-Computer Interfacing.
CoRR, 2023

CryptoMMU: Enabling Scalable and Secure Access Control of Third-Party Accelerators.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

SCALO: An Accelerator-Rich Distributed System for Scalable Brain-Computer Interfacing.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

Imprecise Store Exceptions.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

AstriFlash A Flash-Based System for Online Services.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

Prefetching Using Principles of Hippocampal-Neocortical Interaction.
Proceedings of the 19th Workshop on Hot Topics in Operating Systems, 2023

Mosaic Pages: Big TLB Reach with Small Pages.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

Direct Mind-Machine Teaming (Keynote).
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022
Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation.
J. Electron. Test., 2022

HALO: A Flexible and Low Power Processing Fabric for Brain-Computer Interfaces.
Proceedings of the 2022 IEEE Hot Chips 34 Symposium, 2022

Distill: Domain-Specific Compilation for Cognitive Models.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2022

2021
Balancing Specialized Versus Flexible Computation in Brain-Computer Interfaces.
IEEE Micro, 2021

NBTI-Aware Power Gating Design with Dynamically Varying Stress Probability Control on Sleep Transistor.
J. Circuits Syst. Comput., 2021

Lookup table-based negative-bias temperature instability effect and leakage power co-optimization using genetic algorithm approach.
Int. J. Circuit Theory Appl., 2021

Cognac: Domain-Specific Compilation for Cognitive Models.
CoRR, 2021

Technical perspective: Race logic presents a novel form of encoding.
Commun. ACM, 2021

Paging and the Address-Translation Problem.
Proceedings of the SPAA '21: 33rd ACM Symposium on Parallelism in Algorithms and Architectures, 2021

MIND: In-Network Memory Management for Disaggregated Data Centers.
Proceedings of the SOSP '21: ACM SIGOPS 28th Symposium on Operating Systems Principles, 2021

Rebooting Virtual Memory with Midgard.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

Fast local page-tables for virtualized NUMA servers with vMitosis.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

KLOCs: kernel-level object contexts for heterogeneous memory systems.
Proceedings of the ASPLOS '21: 26th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2021

2020
ECOTLB: Eventually Consistent TLBs.
ACM Trans. Archit. Code Optim., 2020

Biology and Systems Interactions.
IEEE Micro, 2020

Efficient Kernel Object Management for Tiered Memory Systems with KLOC.
CoRR, 2020

SPARTA: A Divide and Conquer Approach to Address Translation for Accelerators.
CoRR, 2020

Hardware-Software Co-Design for Brain-Computer Interfaces.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Mitosis: Transparently Self-Replicating Page-Tables for Large-Memory Machines.
Proceedings of the ASPLOS '20: Architectural Support for Programming Languages and Operating Systems, 2020

2019
Mentions of Security Vulnerabilities on Reddit, Twitter and GitHub.
Proceedings of the 2019 IEEE/WIC/ACM International Conference on Web Intelligence, 2019

Translation ranger: operating system support for contiguity-aware TLBs.
Proceedings of the 46th International Symposium on Computer Architecture, 2019

Nimble Page Management for Tiered Memory Systems.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
Hardware Translation Coherence for Virtualized Systems.
ACM SIGOPS Oper. Syst. Rev., 2018

Breaking the Address Translation Wall by Accelerating Memory Replays.
IEEE Micro, 2018

TLB Shootdown Mitigation for Low-Power Many-Core Servers with L1 Virtual Caches.
IEEE Comput. Archit. Lett., 2018

Scalable Distributed Last-Level TLBs Using Low-Latency Interconnects.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Generic System Calls for GPUs.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Scheduling Page Table Walks for Irregular GPU Applications.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

SEESAW: Using Superpages to Improve VIPT Caches.
Proceedings of the 45th ACM/IEEE Annual International Symposium on Computer Architecture, 2018

Secure, Consistent, and High-Performance Memory Snapshotting.
Proceedings of the Eighth ACM Conference on Data and Application Security and Privacy, 2018

LATR: Lazy Translation Coherence.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
Architectural and Operating System Support for Virtual Memory
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01757-5, 2017

Transistency Models: Memory Ordering at the Hardware-OS Interface.
IEEE Micro, 2017

Preserving Virtual Memory by Mitigating the Address Translation Wall.
IEEE Micro, 2017

GPU System Calls.
CoRR, 2017

VESPA: VIPT Enhancements for Superpage Accesses.
CoRR, 2017

Address Translation Design Tradeoffs for Heterogeneous Systems.
CoRR, 2017

Using branch predictors to predict brain activity in brain-machine implants.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Efficient Address Translation for Architectures with Multiple Page Sizes.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

Translation-Triggered Prefetching.
Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

POSTER: Exploiting Approximations for Energy/Quality Tradeoffs in Service-Based Applications.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

2016
Sweet Spots and Limits for Virtualization.
Proceedings of the 12th ACM SIGPLAN/SIGOPS International Conference on Virtual Execution Environments, 2016

Observations and opportunities in architecting shared virtual memory for heterogeneous systems.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

COATCheck: Verifying Memory Ordering at the Hardware-OS Interface.
Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, 2016

2015
Address Translation for Throughput-Oriented Accelerators.
IEEE Micro, 2015

Large pages and lightweight memory management in virtualized environments: can you have it both ways?
Proceedings of the 48th International Symposium on Microarchitecture, 2015

2014
Increasing TLB reach by exploiting clustering in page translations.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Architectural support for address translation on GPUs: designing memory management units for CPU/GPUs with unified address spaces.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2014

2013
TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs.
ACM Trans. Archit. Code Optim., 2013

Large-reach memory management unit caches.
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

Quantifying and improving I/O predictability in virtualized systems.
Proceedings of the 21st IEEE/ACM International Symposium on Quality of Service, 2013

2012
CoLT: Coalesced Large-Reach TLBs.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

CoScale: Coordinating CPU and Memory System DVFS in Server Systems.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

MultiScale: memory system DVFS with multiple memory controllers.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

2011
Parallelization libraries: Characterizing and reducing overheads.
ACM Trans. Archit. Code Optim., 2011

Shared last-level TLBs for chip multiprocessors.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

2010
Inter-core cooperative TLB for chip multiprocessors.
Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010

2009
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors.
Proceedings of the PACT 2009, 2009

2008
Full-system chip multiprocessor power evaluations using FPGA-based emulation.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008


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