Hyungjin Kim
Orcid: 0000-0002-4834-6882Affiliations:
- Inha University, Department of Electrical Engineering, Incheon, South Korea
- Yeungnam University, Department of Electrical Engineering, Gyeongsan, South Korea (2019 - 2020)
- University of California Santa Barbara, Department of Electrical and Computer Engineering, CA, USA (2018 - 2019)
- Seoul National University, Department of Electrical and Computer Engineering, South Korea (PhD 2017)
According to our database1,
Hyungjin Kim
authored at least 15 papers
between 2012 and 2024.
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Bibliography
2024
Overshoot-Suppressed Memristor Array with AlN Oxygen Barrier for Low-Power Operation in the Intelligent Neuromorphic Systems.
Adv. Intell. Syst., August, 2024
Threshold learning algorithm for memristive neural network with binary switching behavior.
Neural Networks, 2024
2023
Optimization of Random Telegraph Noise Characteristics in Memristor for True Random Number Generator.
Adv. Intell. Syst., May, 2023
Memristor Crossbar Circuit for Ternary Content-Addressable Memory with Fine-Tuning Operation.
Adv. Intell. Syst., March, 2023
2022
4-bit Multilevel Operation in Overshoot Suppressed Al2O3/TiOx Resistive Random-Access Memory Crossbar Array.
Adv. Intell. Syst., 2022
2021
Selected Bit-Line Current PUF: Implementation of Hardware Security Primitive Based on a Memristor Crossbar Array.
IEEE Access, 2021
2020
Digital and Analog Switching Characteristics of InGaZnO Memristor Depending on Top Electrode Material for Neuromorphic System.
IEEE Access, 2020
2019
Towards the Development of Analog Neuromorphic Chip Prototype with 2.4M Integrated Memristors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2013
Novel Tunneling Field-Effect Transistor with Sigma-Shape Embedded SiGe Sources and Recessed Channel.
IEICE Trans. Electron., 2013
2012
Comparative Study on Top- and Bottom-Source Vertical-Channel Tunnel Field-Effect Transistors.
IEICE Trans. Electron., 2012
Effects of Conductive Defects on Unipolar RRAM for the Improvement of Resistive Switching Characteristics.
IEICE Trans. Electron., 2012
Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer).
IEICE Trans. Electron., 2012
Study on Threshold Voltage Control of Tunnel Field-Effect Transistors Using <i>V<sub>T</sub></i>-Control Doping Region.
IEICE Trans. Electron., 2012
Simulation study on scaling limit of silicon tunneling field-effect transistor under tunneling-predominance.
IEICE Electron. Express, 2012