Hyunik Kim
Orcid: 0000-0001-5065-8351
According to our database1,
Hyunik Kim authored at least 9 papers
between 2015 and 2021.
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Bibliography
2021
Proceedings of the Economics of Grids, Clouds, Systems, and Services, 2021
2020
Proceedings of the Economics of Grids, Clouds, Systems, and Services, 2020
Proceedings of the Economics of Grids, Clouds, Systems, and Services, 2020
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020
2018
Proceedings of the 3rd Workshop on System Software for Trusted Execution, 2018
A 0.02mm<sup>2</sup> fully synthesizable period-jitter sensor using stochastic TDC without reference clock and calibration in 10nm CMOS technology.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique.
IEEE J. Solid State Circuits, 2017
2016
19.3 A 2.4GHz 1.5mW digital MDLL using pulse-width comparator and double injection technique in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
14.4 A 5GHz -95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015