Hyojun Kim
Orcid: 0000-0002-9210-5357
According to our database1,
Hyojun Kim
authored at least 45 papers
between 2003 and 2024.
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Bibliography
2024
Amortized Large Look-up Table Evaluation with Multivariate Polynomials for Homomorphic Encryption.
IACR Cryptol. ePrint Arch., 2024
2023
A 43.3-μW Biopotential Amplifier With Tolerance to Common-Mode Interference of 18 V<sub>pp</sub> and T-CMRR of 105 dB in 180-nm CMOS.
IEEE J. Solid State Circuits, February, 2023
IEEE J. Solid State Circuits, 2023
IEEE Access, 2023
Proceedings of the IEEE International Conference on Prognostics and Health Management, 2023
A 0.991JS FFT-Based Fast-Locking, 0.82GHz-to-4.lGHz DPLL-Based lnput-Jitter-Filtering Clock Driver with Wide-Range Mode-Switching 8-Shaped LC Oscillator for DRAM Interfaces.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
BLOCSUM: Block Scope-based Source Code Summarization via Shared Block Representation.
Proceedings of the Findings of the Association for Computational Linguistics: ACL 2023, 2023
2022
A Low-Jitter 8-GHz RO-Based ADPLL With PVT-Robust Replica-Based Analog Closed Loop for Supply Noise Compensation.
IEEE J. Solid State Circuits, 2022
A 100MHz-Reference, 8GHz/16GHz, 177fsrms/223fsrms RO-Based IL-ADPLL Incorporating Reference Octupler with Probability-Based Fast Phase-Error Calibration.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A Supply-Noise-Induced Jitter-Cancelling Clock Distribution Network for LPDDR5 Mobile DRAM featuring a 2nd-order Adaptive Filter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
TABS: Efficient Textual Adversarial Attack for Pre-trained NL Code Model Using Semantic Beam Search.
Proceedings of the 2022 Conference on Empirical Methods in Natural Language Processing, 2022
2021
An Adaptive Offset Cancellation Scheme and Shared-Summer Adaptive DFE for 0.068 pJ/b/dB 1.62-to-10 Gb/s Low-Power Receiver in 40 nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS.
IEEE Access, 2021
28.6 A 22.6µ W Biopotential Amplifier with Adaptive Common-Mode Interference Cancelation Achieving Total-CMRR of 104dB and CMI Tolerance of 15Vpp in 0.18µm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the 2021 IEEE/CVF International Conference on Computer Vision, 2021
2020
A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference.
IEEE J. Solid State Circuits, 2020
Proceedings of the International SoC Design Conference, 2020
A 8.4Gb/s Low Power Transmitter with 1.66 pJ/b using 40: 1 Serializer for DisplayPort Interface.
Proceedings of the International SoC Design Conference, 2020
2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 0.1pJ/b/dB 1.62-to-10.8Gb/s Video Interface Receiver with Fully Adaptive Equalization Using Un-Even Data Level.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2018
A 3.2-GHz Supply Noise-Insensitive PLL Using a Gate-Voltage-Boosted Source-Follower Regulator and Residual Noise Cancellation.
IEEE Trans. Very Large Scale Integr. Syst., 2018
An Ultra-High Input Impedance Analog Front End Using Self-Calibrated Positive Feedback.
IEEE J. Solid State Circuits, 2018
2017
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
Finding Consistency in an Inconsistent World: Towards Deep Semantic Understanding of Scale-out Distributed Databases.
Proceedings of the 8th USENIX Workshop on Hot Topics in Storage and File Systems, 2016
2015
14.4 A 5GHz -95dBc-reference-Spur 9.5mW digital fractional-N PLL using reference-multiplied time-to-digital converter and reference-spur cancellation in 65nm CMOS.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
Evaluating Phase Change Memory for Enterprise Storage Systems: A Study of Caching and Tiering Approaches.
ACM Trans. Storage, 2014
ACM SIGOPS Oper. Syst. Rev., 2014
Proceedings of the International Workshop on Accelerating Data Management Systems Using Modern Processor and Storage Architectures, 2014
How Could a Flash Cache Degrade Database Performance Rather Than Improve It? Lessons to be Learnt from Multi-Tiered Storage.
Proceedings of the 2nd Workshop on Interactions of NVM/Flash with Operating Systems and Workloads, 2014
2013
Proceedings of the IEEE 29th Symposium on Mass Storage Systems and Technologies, 2013
2012
Proceedings of the ACM SIGMETRICS/PERFORMANCE Joint International Conference on Measurement and Modeling of Computer Systems, 2012
Why are state-of-the-art flash-based multi-tiered storage systems performing poorly for HTTP video streaming?
Proceedings of the Network and Operating System Support for Digital Audio and Video Workshop, 2012
2011
Proceedings of the 3rd ACM SOSP Workshop on Networking, 2011
Proceedings of the Second Annual ACM SIGMM Conference on Multimedia Systems, 2011
2009
IEEE Trans. Consumer Electron., 2009
J. Syst. Softw., 2009
Proceedings of the 29th IEEE International Conference on Distributed Computing Systems (ICDCS 2009), 2009
2008
Proceedings of the 6th USENIX Conference on File and Storage Technologies, 2008
2007
Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007
Proceedings of the Computational Science and Its Applications, 2007
2006
Virtual-ROM: A New Demand Paging Component for RTOS and NAND Flash Memory Based Mobile Devices.
Proceedings of the Computer and Information Sciences, 2006
Proceedings of the 3rd IEEE Consumer Communications and Networking Conference, 2006
2003
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003