NSTherm: An Error-Bounded Network-Stochastic Fusion Thermal Simulator for Geometry-Adaptable Chiplets via Diffeomorphic Mapping and Neural-Guided Variance Reduction.

[BibT_eX]

[DOI]

Yuan Meng

Yuyan Wang

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

LCTMwalk: GPU-Accelerated Transient Thermal Simulation for Liquid-Cooled 2.5D/3D ICs via Random Walks on Circuit Networks of Modified Compact Thermal Models.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

DAMIL-DCIM: A Digital CIM Layout Synthesis Framework with Dataflow-Aware Floorplan and MILP-Based Detailed Placement.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference, 2025

ELMap: Area-Driven LUT Mapping with $k$-LUT Network Exact Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference, 2025

Decoupling Analog Circuit Representation from Technology for Behavior-Centric Optimization.

[BibT_eX]

[DOI]

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

MARIO: A Superadditive Multi-Algorithm Interworking Optimization Framework for Analog Circuit Sizing.

[BibT_eX]

[DOI]

Proceedings of the 62nd ACM/IEEE Design Automation Conference, 2025

2024

LLM-Enhanced Bayesian Optimization for Efficient Analog Layout Constraint Generation.

[BibT_eX]

[DOI]

CoRR, 2024

The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models.

[BibT_eX]

[DOI]

Evangeline F. Y. Young

CoRR, 2024

Erratum to: Large circuit models: opportunities and challenges.

[BibT_eX]

[DOI]

Evangeline F. Y. Young

Sci. China Inf. Sci., 2024

Large circuit models: opportunities and challenges.

[BibT_eX]

[DOI]

Evangeline F. Y. Young

Sci. China Inf. Sci., 2024

Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells.

[BibT_eX]

[DOI]

Proceedings of the 2024 International Symposium on Physical Design, 2024

Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

Revisiting sensitivity-based analog sizing with derivative-aware Bayesian optimization and error-suppressed adjoint analysis.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design, 2024

A Data-Driven Analog Circuit Synthesizer with Automatic Topology Selection and Sizing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Performance-driven Analog Routing via Heterogeneous 3DGNN and Potential Relaxation.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper).

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

A Study on Exploring and Exploiting the High-dimensional Design Space for Analog Circuit Design Automation : (Invited Paper).

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

ISOP-Yield: Yield-Aware Stack-Up Optimization for Advanced Package using Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

Tutorial and Perspectives on MAGICAL: A Silicon-Proven Open-Source Analog IC Layout System.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, February, 2023

Hierarchical Analog and Mixed-Signal Circuit Placement Considering System Signal Flow.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Joint Optimization of Sizing and Layout for AMS Designs: Challenges and Opportunities.

[BibT_eX]

[DOI]

Proceedings of the 2023 International Symposium on Physical Design, 2023

Reinforcement Learning Guided Detailed Routing for Custom Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2023 International Symposium on Physical Design, 2023

AlphaSyn: Logic Synthesis Optimization with Efficient Monte Carlo Tree Search.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Practical Layout-Aware Analog/Mixed-Signal Design Automation with Bayesian Neural Networks.

[BibT_eX]

[DOI]

Ahmet Faruk Budak

Keren Zhu

David Z. Pan

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

ISOP: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package Design.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

AutoCRAFT: Layout Automation for Custom Circuits in Advanced FinFET Technologies.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

Fuse and Mix: MACAM-Enabled Analog Activation for Energy-Efficient Neural Acceleration.

[BibT_eX]

[DOI]

Jean Anne C. Incorvia

David Z. Pan

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

TAG: Learning Circuit Spatial Embedding from Layouts.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Reinforcement Learning for Electronic Design Automation: Case Studies and Perspectives: (Invited Paper).

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

Automating Analog Constraint Extraction: From Heuristics to Learning: (Invited Paper).

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

MAGICAL: An Open- Source Fully Automated Analog IC Layout System from Netlist to GDSII.

[BibT_eX]

[DOI]

IEEE Des. Test, 2021

Optimizer Fusion: Efficient Training with Better Locality and Parallelism.

[BibT_eX]

[DOI]

CoRR, 2021

OpenSAR: An Open Source Automated End-to-end SAR ADC Compiler.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Universal Symmetry Constraint Extraction for Analog and Mixed-Signal Circuits with Graph Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

An In-Memory-Computing Charge-Domain Ternary CNN Classifier.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

MAGICAL 1.0: An Open-Source Fully-Automated AMS Layout Synthesis Framework Verified With a 40-nm 1GS/s Δ∑ ADC.

[BibT_eX]

[DOI]

Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020

Exploring Logic Optimizations with Reinforcement Learning and Graph Convolutional Network.

[BibT_eX]

[DOI]

Proceedings of the MLCAD '20: 2020 ACM/IEEE Workshop on Machine Learning for CAD, 2020

Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Effective Analog/Mixed-Signal Circuit Placement Considering System Signal Flow.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

An Efficient Training Framework for Reversible Neural Architectures.

[BibT_eX]

[DOI]

Proceedings of the Computer Vision - ECCV 2020, 2020

Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer Learning.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

S<sup>3</sup>DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

MAGICAL: Toward Fully Automated Analog IC Layout Leveraging Human and Machine Intelligence: Invited Paper.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

Keren Zhu

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