Ja-Hoon Jin
Orcid: 0000-0001-7012-9991
According to our database1,
Ja-Hoon Jin
authored at least 10 papers
between 2014 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization.
IEEE J. Solid State Circuits, January, 2024
2023
A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
IEEE Access, 2022
A 3nm GAAFET Analog Assisted Digital LDO with High Current Density for Dynamic Voltage Scaling Mobile Applications.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
2020
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2020
2018
A 12.5-Gb/s Near-Ground Transceiver Employing a MaxEye Algorithm-Based Adaptation Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2018
A 0.75-3.0-Gb/s Dual-Mode Temperature-Tolerant Referenceless CDR With a Deadzone-Compensated Frequency Detector.
IEEE J. Solid State Circuits, 2018
A 4.0-10.0-Gb/s Referenceless CDR with Wide-Range, Jitter-Tolerant, and Harmonic-Lock-Free Frequency Acquisition Technique.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014