Hyuntak Jeon

Orcid: 0000-0003-0537-8494

According to our database1, Hyuntak Jeon authored at least 14 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A Sub-aF Super-High-Resolution Capacitance-to-Digital Converter with a Bandpass ΔΣ ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
A Wide-Dynamic-Range Neural-Recording IC With Automatic-Gain-Controlled AFE and CT Dynamic-Zoom ΔΣ ADC for Saturation-Free Closed-Loop Neural Interfaces.
IEEE J. Solid State Circuits, 2022

An SRAM-Based Hybrid Computation-in-Memory Macro Using Current-Reused Differential CCO.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

2021
A SiPM Readout IC Embedded in a Boost Converter for Mobile Dosimeters.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

A Self-Powered Wireless Gas Sensor Node Based on Photovoltaic Energy Harvesting.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

A 99.5dB-DR 5kHz-BW Closed-Loop Neural-Recording IC based on Continuous-Time Dynamic-Zoom ΔΣ ADC with Automatic AFE-Gain Control.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
A CMRR Enhancement Circuit Employing Gₘ-Controllable Output Stages for Capacitively Coupled Instrumentation Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

A Power-Efficient Radiation Sensor Interface with a Peak-Triggered Sampling Scheme for Mobile Dosimeters.
Sensors, 2020

2019
A High DR, DC-Coupled, Time-Based Neural-Recording IC With Degeneration R-DAC for Bidirectional Neural Interface.
IEEE J. Solid State Circuits, 2019

A 100Mb/s Galvanically-Coupled Body-Channel-Communication Transceiver with 4.75pJ/b TX and 26.8 pJ/b RX for Bionic Arms.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018
6.5µW 92.3DB-DR Biopotential-Recording Front-End with 360MVPP Linear Input Range.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 650-uW 30-Mbps Galvanic Coupling Communication Receiver for Bionic Arms.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A 3.9μW, 81.3dB SNDR, DC-coupled, Time-based Neural Recording IC with Degeneration R-DAC for Bidirectional Neural Interface in 180nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A neural recording amplifier based on adaptive SNR optimization technique for long-term implantation.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017


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