Sein Oh

Orcid: 0000-0003-0759-5302

According to our database1, Sein Oh authored at least 16 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
A 187-dB FoM<sub>S</sub> Power-Efficient Second-Order Highpass ΔΣ Capacitance-to-Digital Converter.
IEEE J. Solid State Circuits, April, 2024

33.8 A Two-Electrode Bio-Impedance Readout IC with Complex-Domain Noise-Correlated Baseline Cancellation Supporting Sinusoidal Excitation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
A Sub-GHz CMOS SPDT Antenna Switch Employing Linearity-Enhanced Biasing Strategy for Second-Order Harmonic Reduction.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023

A High-Efficiency Single-Mode Dual-Path Buck-Boost Converter With Reduced Inductor Current.
IEEE J. Solid State Circuits, March, 2023

A 2.5mW 12MHz-BW 69dB SNDR Passive Bandpass ΔΣ ADC with Highpass Noise-Shaping SAR Quantizers.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A 187dB FoMS 46fJ/Conv 2<sup>nd</sup>-order Highpass Δ∑ Capacitance-to-Digital Converter.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

A Sub-aF Super-High-Resolution Capacitance-to-Digital Converter with a Bandpass ΔΣ ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A 56fJ/Conversion-Step 178dB-FoMS Third-Order Hybrid CT-DT Δ∑ Capacitance-to-Digital Converter.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
A Single-Mode Dual-Path Buck-Boost Converter with Reduced Inductor Current Across All Duty Cases Achieving 95.58% Efficiency at 1A in Boost Operation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021
An 85 dB DR 4 MHz BW Pipelined Noise-Shaping SAR ADC With 1-2 MASH Structure.
IEEE J. Solid State Circuits, 2021

An 8MHz 31.25kS/s Impedance-Monitoring IC Based on IF-Sampling Architecture with a Band-Pass Delta-Sigma ADC.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

A Load-Current-Regulating OLED Lamp Driver Using a Hybrid Step-Up Converter with 93.21% Efficiency at a High Conversion Ratio of 4.1.
Proceedings of the 47th ESSCIRC 2021, 2021

2020
Low Power CMOS-Based Hall Sensor with Simple Structure Using Double-Sampling Delta-Sigma ADC.
Sensors, 2020

A 80dB DR 6MHz Bandwidth Pipelined Noise-Shaping SAR ADC with 1-2 MASH structure.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
4-Contact structure of vertical-type CMOS Hall device for 3-D magnetic sensor.
IEICE Electron. Express, 2019

2018
A 3D-Printed Multichannel Viscometer for High-Throughput Analysis of Frying Oil Quality.
Sensors, 2018


  Loading...