Chul Kim

Orcid: 0000-0002-2927-5740

According to our database1, Chul Kim authored at least 79 papers between 1994 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2024
DiTTO: A Distance Adaptive Over 100-mW Wireless Power Transfer System With 1.695-Mb/s Uplink Telemetry and a Shared Inductor Two-Output Regulating Rectification.
IEEE J. Solid State Circuits, August, 2024

2023
A High-Efficiency Single-Mode Dual-Path Buck-Boost Converter With Reduced Inductor Current.
IEEE J. Solid State Circuits, March, 2023

2022
The Secret to Finding a Match: A Field Experiment on Choice Capacity Design in an Online Dating Platform.
Inf. Syst. Res., December, 2022

An Intra-Body Power Transfer System With $>$1-mW Power Delivered to the Load and 3.3-V DC Output at 160-cm of on-Body Distance.
IEEE Trans. Biomed. Circuits Syst., 2022

Seamless Capacitive Body Channel Wireless Power Transmission Toward Freely Moving Multiple Animals in an Animal Cage.
IEEE Trans. Biomed. Circuits Syst., 2022

A 96.5%-Power-Efficiency Hybrid Buck-Boost Photovoltaic Energy Harvester Employing Adaptive FOCV MPPT Control for >98% MPPT Efficiency Across a 10, 000× Dynamic Range.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A Single-Mode Dual-Path Buck-Boost Converter with Reduced Inductor Current Across All Duty Cases Achieving 95.58% Efficiency at 1A in Boost Operation.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

Zero-Weight aware LSTM Architecture for Edge-Level EEG Classification.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022

2021
Energy-Efficient High-Voltage Pulsers for Ultrasound Transducers.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Wireless Power and Data Transfer IC for Neural Prostheses Using a Single Inductive Link With Frequency-Splitting Characteristic.
IEEE Trans. Biomed. Circuits Syst., 2021

Guest Editorial Special Issue on Selected Papers From IEEE ISCAS 2020.
IEEE Trans. Biomed. Circuits Syst., 2021

An Optically Addressed Nanowire-Based Retinal Prosthesis With Wireless Stimulation Waveform Control and Charge Telemetering.
IEEE J. Solid State Circuits, 2021

A 96.6%-Efficiency Continuous-Input-Current Hybrid Dual-Path Buck-Boost Converter with Single-Mode Operation and Non-Stopping Output Current Delivery.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

A Self-Powered Wireless Gas Sensor Node Based on Photovoltaic Energy Harvesting.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

A Frequency-Splitting-Based Wireless Power and Data Transfer IC for Neural Prostheses with Simultaneous 115mWPower and 2.5Mb/s Forward Data Delivery.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

34.4 An Energy-Replenishing Ultrasound Pulser with 0.25CV<sup>2</sup> f Dynamic Power Consumption.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

18.1 An Optically-Addressed Nanowire-Based Retinal Prosthesis with 73% RF-to-Stimulation Power Efficiency and 20nC-to-3μ C Wireless Charge Telemetering.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

A Load-Current-Regulating OLED Lamp Driver Using a Hybrid Step-Up Converter with 93.21% Efficiency at a High Conversion Ratio of 4.1.
Proceedings of the 47th ESSCIRC 2021, 2021

Low-Power 256-Channel Nanowire Electrode-on-Chip Neural Interface for Intracellular Electrophysiology.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021

2020
Modeling Dynamics in Crowdfunding.
Mark. Sci., 2020

1024-Electrode Hybrid Voltage/Current-Clamp Neural Interface System-on-Chip with Dynamic Incremental-SAR Acquisition.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A 0.0046mm<sup>2</sup> 6.7μW Three-Stage Amplifier Capable of Driving 0.5-to-1.9nF Capacitive Load with >0.68MHz GBW without Compensation Zero.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

A 4.2-pJ/Conv 10-b Asynchronous ADC with Hybrid Two-Tier Level-Crossing Event Coding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Are More Choices Better? Examining the Impact of Choice Capacity in Online Dating Platform.
Proceedings of the 41st International Conference on Information Systems, 2020

2019
Digitally Adaptive High-Fidelity Analog Array Signal Processing Resilient to Capacitive Multiplying DAC Inter-Stage Gain Error.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 3 mm × 3 mm Fully Integrated Wireless Power Receiver and Neural Interface System-on-Chip.
IEEE Trans. Biomed. Circuits Syst., 2019

A Fully Integrated RF-Powered Energy-Replenishing Current-Controlled Stimulator.
IEEE Trans. Biomed. Circuits Syst., 2019

Patient-Provider Interaction System for Efficient Home-Based Cardiac Rehabilitation Exercise.
IEEE Access, 2019

A Study on Features for Improving Performance of Chinese OCR by Machine Learning.
Proceedings of the 2019 3rd High Performance Computing and Cluster Technologies Conference (HPCCT 2019) and of the 2nd International Conference on Big Data and Artificial Intelligence (BDAI 2019), Guangzhou, China, June 22, 2019

Online Monitoring Automation Using Anomaly Detection in IoT/IT Environment.
Proceedings of the Artificial Intelligence Methods in Intelligent Algorithms, 2019

2018
Sub-µV<sub>rms</sub>-Noise Sub-µW/Channel ADC-Direct Neural Recording With 200-mV/ms Transient Recovery Through Predictive Digital Autoranging.
IEEE J. Solid State Circuits, 2018

A 500-MHz Bandwidth 7.5-mV<sub>pp</sub> Ripple Power-Amplifier Supply Modulator for RF Polar Transmitters.
IEEE J. Solid State Circuits, 2018

A 92dB dynamic range sub-μVrms-noise 0.8μW/ch neural-recording ADC array with predictive digital autoranging.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Implementation of Superconducting Cables in Medium Voltage DC Integrated Power Systems on All Electric Ships.
Proceedings of the IECON 2018, 2018

2017
Silicon-Integrated High-Density Electrocortical Interfaces.
Proc. IEEE, 2017

A 144-MHz Fully Integrated Resonant Regulating Rectifier With Hybrid Pulse Modulation for mm-Sized Implants.
IEEE J. Solid State Circuits, 2017

21.7 2pJ/MAC 14b 8×8 linear transform mixed-signal spatial filter in 65nm CMOS with 84dB interference suppression.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Design of miniaturized wireless power receivers for mm-sized implants.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

From algorithms to devices: Enabling machine learning through ultra-low-power VLSI mixed-signal array processing.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

Wireless powering of mm-scale fully-on-chip neural interfaces.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

2016
A 6.5-µW/MHz Charge Buffer With 7-fF Input Capacitance in 65-nm CMOS for Noncontact Electropotential Sensing.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

A 1.3 mW 48 MHz 4 Channel MIMO Baseband Receiver With 65 dB Harmonic Rejection and 48.5 dB Spatial Signal Separation.
IEEE J. Solid State Circuits, 2016

Energy Recycling Telemetry IC With Simultaneous 11.5 mW Power and 6.78 Mb/s Backward Data Delivery Over a Single 13.56 MHz Inductive Link.
IEEE J. Solid State Circuits, 2016

A fully integrated 144 MHz wireless-power-receiver-on-chip with an adaptive buck-boost regulating rectifier and low-loss H-Tree signal distribution.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

A 6μW/MHz charge buffer with 7fF input capacitance in 65nm CMOS for non-contact electropotential sensing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
A CMOS 4-channel MIMO baseband receiver with 65dB harmonic rejection over 48MHz and 50dB spatial signal separation over 3MHz at 1.3mW.
Proceedings of the Symposium on VLSI Circuits, 2015

A 144MHz integrated resonant regulating rectifier with hybrid pulse modulation.
Proceedings of the Symposium on VLSI Circuits, 2015

A 16-channel wireless neural interfacing SoC with RF-powered energy-replenishing adiabatic stimulation.
Proceedings of the Symposium on VLSI Circuits, 2015

A Log Regression Seasonality Based Approach for Time Series Decomposition Prediction in System Resources.
Proceedings of the Advances in Computer Science and Ubiquitous Computing, 2015

2014
PSR Enhancement Through Super Gain Boosting and Differential Feed-Forward Noise Cancellation in a 65-nm CMOS LDO Regulator.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Integrated Circuits and Electrode Interfaces for Noninvasive Physiological Monitoring.
IEEE Trans. Biomed. Eng., 2014

Energy-recycling integrated 6.78-Mbps data 6.3-mW power telemetry over a single 13.56-MHz inductive link.
Proceedings of the Symposium on VLSI Circuits, 2014

A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS.
Proceedings of the ESSCIRC 2014, 2014

A 12.6 mW 8.3 Mevents/s contrast detection 128×128 imager with 75 dB intra-scene DR asynchronous random-access digital readout.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Picking out herbs with analogous efficacy based on MeSH semantic similarity.
Proceedings of the 2014 IEEE International Conference on Bioinformatics and Biomedicine, 2014

Whole cancer genome analysis using an I/O aware job scheduler on high performance computing resource.
Proceedings of the 2014 IEEE International Conference on Bioinformatics and Biomedicine, 2014

2012
A CMOS LDO regulator with high PSR using Gain Boost-Up and Differential Feed Forward Noise Cancellation in 65nm process.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
A low-power small-area open loop digital DLL for 2.2Gb/s/pin 2Gb DDR3 SDRAM.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
Design of a Tunable All-Digital UWB Pulse Generator CMOS Chip for Wireless Endoscope.
IEEE Trans. Biomed. Circuits Syst., 2010

Modeling of Energy-efficient Applicable Routing Algorithm in WSN.
J. Digit. Content Technol. its Appl., 2010

Ontology for medicinal materials based on traditional Korean medicine.
Bioinform., 2010

A 105dB-gain 500MHz-bandwidth 0.1Ω-output-impedance amplifier for an amplitude modulator in 65nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008
Media Access Time-Rearrangement of Wireless LAN for a Multi-Radio Collocated Platform.
IEICE Trans. Commun., 2008

Proactive Time-Rearrangement Scheme for Multi-Radio Collocated Platform.
IEICE Trans. Commun., 2008

Temporal Ontology Language for Representing and Reasoning Interval-Based Temporal Knowledge.
Proceedings of the Semantic Web, 3rd Asian Semantic Web Conference, 2008

2007
Survey and Analysis about the Level of Teachers' Abilities of Using Information and Communication Technology.
Proceedings of the 11th International Conference on Computer Supported Cooperative Work in Design, 2007

2006
3D-SoftChip: A Novel Architecture for Next-Generation Adaptive Computing Systems.
EURASIP J. Adv. Signal Process., 2006

2005
3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

3D-SoftChip: a novel 3D vertically integrated adaptive computing system (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004
SOC-B Design and Testing Technique of IS-95C CDMA Transmitter for Measurement of Electric Field Intensity using FPGA and ASIC.
Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

2002
Hierarchical Restoration Scheme for Multiple Failures in GMPLS Networks.
Proceedings of the 31st International Conference on Parallel Processing Workshops (ICPP 2002 Workshops), 2002

Design and Implementation of a Web-Based Classroom Management Support System for Elementary School Classroom Management.
Proceedings of the International Conference on Computers in Education, 2002

2001
On a Network Security Model for the Secure Information Flow on Multilevel Secure Network.
Proceedings of the Information and Communications Security, Third International Conference, 2001

1999
A Note on Similarity Measures between Vague Sets and between Elements.
Inf. Sci., 1999

1998
On the Security of the Hashing Scheme Based on SL<sub>2</sub>.
Proceedings of the Fast Software Encryption, 5th International Workshop, 1998

1997
Fuzzy neurons and fuzzy multilinear mappings.
Proceedings of International Conference on Neural Networks (ICNN'97), 1997

1995
Configuring Multiple Boundary Scan Chains for Board Testing.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Exploitation of parallelism in group probing for testing massively parallel processing systems.
Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994
Test sequence generation methods for protocol conformance testing.
Proceedings of the Eighteenth Annual International Computer Software and Applications Conference, 1994


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