Junghyup Lee

According to our database1, Junghyup Lee authored at least 17 papers between 2006 and 2020.

Collaborative distances:



In proceedings 
PhD thesis 


On csauthors.net:


An Ultra-Low-Noise Swing-Boosted Differential Relaxation Oscillator in 0.18-μm CMOS.
IEEE J. Solid State Circuits, 2020

A Multi-Mode ULP Receiver Based on an Injection-Locked Oscillator for IoT Applications.
IEEE Access, 2020

A 1.0 V, 5.4 pJ/bit GFSK Demodulator Based on an Injection Locked Ring Oscillator for Low-IF Receivers.
IEEE Access, 2020

Learning with Privileged Information for Efficient Image Super-Resolution.
Proceedings of the Computer Vision - ECCV 2020, 2020

Learning Semantic Correspondence Exploiting an Object-level Prior.
CoRR, 2019

SFNet: Learning Object-Aware Semantic Correspondence.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2019

A 114-AF RMS- Resolution 46-NF/10-MΩ -Range Digital-Intensive Reconfigurable RC-to-Digital Converter with Parasitic-Insensitive Femto-Farad Baseline Sensing.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

A 110dB-CMRR 100dB-PSRR multi-channel neural-recording amplifier system using differentially regulated rejection ratio enhancement in 0.18μm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A Wearable Electrocardiogram Monitoring System Robust to Motion Artifacts.
Proceedings of the International SoC Design Conference, 2018

An ultra-low-noise differential relaxation oscillator based on a swing-boosting scheme.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

A 1 V 2.5 μW fully-differential ASK demodulator with 12.5 pJ/bit FOM for ultra-low power biomedical applications.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A neural recording amplifier based on adaptive SNR optimization technique for long-term implantation.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

5.10 A 1.4V 10.5MHz swing-boosted differential relaxation oscillator with 162.1dBc/Hz FOM and 9.86psrms period jitter in 0.18µm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

5.10 A 4.7MHz 53μW fully differential CMOS reference clock oscillator with -22dB worst-case PSNR for miniaturized SoCs.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

30.7 A 60Mb/s wideband BCC transceiver with 150pJ/b RX and 31pJ/b TX for emerging wearable applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A 1.4-µW 24.9-ppm/°C Current Reference With Process-Insensitive Temperature Compensation in 0.18-µm CMOS.
IEEE J. Solid State Circuits, 2012

Power Analysis of VLSI Interconnect with RLC Tree Models and Model Reduction.
J. Circuits Syst. Comput., 2006