Jason D. Bakos

Orcid: 0000-0002-0821-6258

According to our database1, Jason D. Bakos authored at least 39 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
NAPOLY: A Non-deterministic Automata Processor OverLaY.
ACM Trans. Reconfigurable Technol. Syst., September, 2023

Optimal Sampling Methodologies for High-rate Structural Twinning.
Proceedings of the 26th International Conference on Information Fusion, 2023

FPGA Processor In Memory Architectures (PIMs): Overlay or Overhaul ?
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Accelerating LSTM-Based High-Rate Dynamic System Models.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Making BRAMs Compute: Creating Scalable Computational Memory Fabric Overlays.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

2022
High-Rate Machine Learning for Forecasting Time-Series Signals.
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

2019
An Overlay Architecture for Pattern Matching.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

OpenVX Graph Optimization for Visual Processor Units.
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018
Introduction to the Special Section on FCCM'16.
ACM Trans. Reconfigurable Technol. Syst., 2018

2017
A Dynamically Reconfigurable Automata Processor Overlay.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017

2016
High-level synthesis of a genomic database search engine.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016

Two-Hit Filter Synthesis for Genomic Database Search.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2015
Memory Interface Design for 3D Stencil Kernels on a Massively Parallel Memory System.
ACM Trans. Reconfigurable Technol. Syst., 2015

2014
Large-Scale Pairwise Sequence Alignments on a Large-Scale GPU Cluster.
IEEE Des. Test, 2014

Lucas-Kanade Optical Flow estimation on the TI C66x digital signal processor.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014

Sparse matrix-vector multiply on the Keystone II Digital Signal Processor.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2014

2013
An FPGA-Based Accelerator for Frequent Itemset Mining.
ACM Trans. Reconfigurable Technol. Syst., 2013

Accelerating frequent itemset mining on graphics processing units.
J. Supercomput., 2013

A Heuristic Scheduler for Port-Constrained Floating-Point Pipelines.
Int. J. Reconfigurable Comput., 2013

Extending the BEAGLE library to a multi-FPGA platform.
BMC Bioinform., 2013

Accuracy, cost, and performance tradeoffs for floating-point accumulation.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Memory Access Scheduling on the Convey HC-1.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Sparse matrix-vector multiply on the Texas Instruments C6678 Digital Signal Processor.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
A Cluster-on-a-Chip Architecture for High-Throughput Phylogeny Search.
IEEE Trans. Parallel Distributed Syst., 2012

2011
A Sparse Matrix Personality for the Convey HC-1.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

GPApriori: GPU-Accelerated Frequent Itemset Mining.
Proceedings of the 2011 IEEE International Conference on Cluster Computing (CLUSTER), 2011

Frequent Itemset Mining on Large-Scale Shared Memory Machines.
Proceedings of the 2011 IEEE International Conference on Cluster Computing (CLUSTER), 2011

2010
High-Performance Heterogeneous Computing with the Convey HC-1.
Comput. Sci. Eng., 2010

FPGA acceleration of the phylogenetic likelihood function for Bayesian MCMC inference methods.
BMC Bioinform., 2010

2009
An integrated reduction technique for a double precision accumulator.
Proceedings of the Third International Workshop on High-Performance Reconfigurable Computing Technology and Applications, 2009

Exploiting Matrix Symmetry to Improve FPGA-Accelerated Conjugate Gradient.
Proceedings of the FCCM 2009, 2009

2008
A Special-Purpose Architecture for Solving the Breakpoint Median Problem.
IEEE Trans. Very Large Scale Integr. Syst., 2008

2007
Lightweight Error Correction Coding for System-Level Interconnects.
IEEE Trans. Computers, 2007

FPGA Acceleration of Gene Rearrangement Analysis.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

FPGA Acceleration of Phylogeny Reconstruction for Whole Genome Data.
Proceedings of the 7th IEEE International Conference on Bioinformatics and Bioengineering, 2007

2006
Predictive Load Balancing for Interconnected FPGAs.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A Reconfigurable Distributed Computing Fabric Exploiting Multilevel Parallelism.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

2005
Area, power, and pin efficient bus transceiver using multi-bit-differential signaling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Active substrates for optoelectronic interconnect.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


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