Donald M. Chiarulli

According to our database1, Donald M. Chiarulli authored at least 49 papers between 1984 and 2017.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Group Scissor: Scaling Neuromorphic Computing Design to Large Neural Networks.
Proceedings of the 54th Annual Design Automation Conference, 2017

Enabling New Computation Paradigms with HyperFET - An Emerging Device.
IEEE Trans. Multi-Scale Computing Systems, 2016

A Simplified Phase Model for Simulation of Oscillator-Based Computing Systems.
JETC, 2016

A Visual Attention Algorithm Designed for Coupled Oscillator Acceleration.
Proceedings of the 2016 IEEE Conference on Computer Vision and Pattern Recognition Workshops, 2016

A Simplified Phase Model for Oscillator Based Computing.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

A Computational Primitive for Convolution based on Coupled Oscillator Arrays.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

HMAX image processing pipeline with coupled oscillator acceleration.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

Computational Architectures Based on Coupled Oscillators.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Modeling oscillator arrays for video analytic applications.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Feature-aided multiple-hypothesis tracking and classification of biological cells.
Proceedings of the 17th International Conference on Information Fusion, 2014

Dielectrophoresis-based classification of cells using multi-target multiple-hypothesis tracking.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

Video analytics using beyond CMOS devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Associative processing with coupled oscillators.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Scalable arbitration of partitioned bus interconnection networks in 3D-IC systems.
Proceedings of the Second International Workshop on Network on Chip Architectures, 2009

Massively parallel processing: it's déjà vu all over again.
Proceedings of the 46th Design Automation Conference, 2009

A routerless system level interconnection network for 3D integrated systems.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

3D integrated circuits for lab-on-chip applications.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Lightweight Error Correction Coding for System-Level Interconnects.
IEEE Trans. Computers, 2007

Non-Linear Circuit Simulation using MATLAB.
Proceedings of the Forum on specification and Design Languages, 2007

Nonlinear model order reduction using remainder functions.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Area, power, and pin efficient bus transceiver using multi-bit-differential signaling.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

High-Speed Optoelectronics Receivers in SiGe.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Active substrates for optoelectronic interconnect.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An Application of Parallel Discrete Event Simulation Algorithms to Mixed Domain System Simulation.
Proceedings of the 2004 Design, 2004

System simulation of mixed-signal multi-domain microsystems with piecewise linear models.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

Short Courses in System-on-a-Chip (SoC) Design.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

A fast optical propagation technique for modeling micro-optical systems.
Proceedings of the 39th Design Automation Conference, 2002

Optoelectronic Multi-chip Modules Based on Imaging Fiber Bundle Structures.
Proceedings of the Parallel and Distributed Processing, 2000

A CAD Tool for Optical MEMS.
Proceedings of the 36th Conference on Design Automation, 1999

Reconfigurable Processor Architectures Exploiting High Bandwidth Optical Channels.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

Characterization of CMOS Defects using Transient Signal Analysis.
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

Identification of Defective CMOS Devices Using Correlation and Regression Analysis of Frequency Domain Transient Signal Data.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

Predicting Multiprocessor Memory Access Patterns with Learning Models.
Proceedings of the Fourteenth International Conference on Machine Learning (ICML 1997), 1997

Computer-Aided Design of Free-Space Opto-Electronic Systems.
Proceedings of the 34st Conference on Design Automation, 1997

Digital Integrated Circuit Testing using Transient Signal Analysis.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

The Partitioned Optical Passive Stars (POPS) topology.
Proceedings of IPPS '95, 1995

Dynamic Reconfiguration of Optically Interconnected Networks with Time-Division Multiplexing .
J. Parallel Distrib. Comput., 1994

Optical Computing and Interconnection Systems - Guest Editors' Introduction.
J. Parallel Distrib. Comput., 1993

Pipelined Communications in Optically Interconnected Arrays.
J. Parallel Distrib. Comput., 1991

Multicasting in Optical Bus Connected Processors Using Coincident Pulse Techniques.
Proceedings of the International Conference on Parallel Processing, 1991

Optical Bus Control for Distributed Multiprocessors.
J. Parallel Distrib. Comput., 1990

Timing Verification Using HDTV.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

Space Multiplexing of Waveguides in Optically Interconnected Multiprocessor Systems.
Comput. J., 1989

Using Coincident Optical Pulses for Parallel Memory Addressing.
IEEE Computer, 1987

Parallel microprogramming tools for a horizontally reconfigurable architecture.
International Journal of Parallel Programming, 1986

Parallel Processing of Quadtrees on a Horizontally Reconfigurable Architecture Computing System.
Proceedings of the International Conference on Parallel Processing, 1986

DRAFT: A dynamically reconfigurable processor for integer arithmetic.
Proceedings of the 7th IEEE Symposium on Computer Arithmetic, 1985

DRAFT (abstract only): Dynamically Reconfigurable Architecture for Factoring Tests.
Proceedings of the 13th ACM Annual Conference on Computer Science, 1985

A High Performance Factoring Machine.
Proceedings of the 11th Annual Symposium on Computer Architecture, 1984