Jay Jahangiri

According to our database, Jay Jahangiri authored at least 6 papers between 2005 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2014

Test Compression Improvement with EDT Channel Sharing in SoC Designs.

Yu Huang, Mark Kassab, Jay Jahangiri, Janusz Rajski, Wu-Tung Cheng, Dongkwan Han, Jihye Kim, Kun Young Chung

Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

2007

Silicon Evaluation of Static Alternative Fault Models.

Chris Schuermyer, Jewel Pangilinan, Jay Jahangiri, Martin Keim, Janusz Rajski, Brady Benware

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

2006

The Demand and Practical Approach for 100x Test Compression.

Ron Press, Jay Jahangiri

Proceedings of the IFIP VLSI-SoC 2006, 2006

2005

Value-Added Defect Testing Techniques.

Jay Jahangiri, David Abercrombie

IEEE Des. Test Comput., 2005

Meeting Nanometer DPM Requirements Through DFT.

Jay Jahangiri, David Abercrombie

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Achieving High Test Quality with Reduced Pin Count Testing.

Jay Jahangiri, Nilanjan Mukherjee, Wu-Tung Cheng, Subramanian Mahadevan, Ron Press

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005