Kun Young Chung

According to our database1, Kun Young Chung authored at least 9 papers between 2003 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Industry Evaluation of Reversible Scan Chain Diagnosis.
Proceedings of the IEEE International Test Conference, 2022

2017
Innovative practices session 9C DFT and data for diagnostics.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

2016
Comprehensive optimization of scan chain timing during late-stage IC implementation.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Learning-based prediction of embedded memory timing failures during initial floorplan design.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2014
Test Compression Improvement with EDT Channel Sharing in SoC Designs.
Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

2010
Design and test of latch-based circuits to maximize performance, yield, and delay test quality.
Proceedings of the 2011 IEEE International Test Conference, 2010

2009
Efficient Scheduling of Path Delay Tests for Latch-Based Circuits.
Proceedings of the 27th IEEE VLSI Test Symposium, 2009

2006
Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

2003
Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003


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