Jayanth Gopinath

Orcid: 0009-0006-8137-1250

According to our database1, Jayanth Gopinath authored at least 4 papers between 2021 and 2023.

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Bibliography

2023
DEFending Integrated Circuit Layouts.
IACR Cryptol. ePrint Arch., 2023

HAAC: A Hardware-Software Co-Design to Accelerate Garbled Circuits.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

2022
Benchmarking Security Closure of Physical Layouts: ISPD 2022 Contest.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

2021
Security Closure of Physical Layouts ICCAD Special Session Paper.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021


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