Jesse Simonsson

According to our database, Jesse Simonsson authored at least 3 papers between 2015 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2020

A 0.4-0.9V, 2.87pJ/cycle Near-Threshold ARM Cortex-M3 CPU with In-Situ Monitoring and Adaptive-Logic Scan.

Markus Hiienkari, Navneet Gupta, Jukka Teittinen, Jesse Simonsson, Matthew J. Turnquist, Jonas Eriksson, Risto Anttila, Ohto Myllynen, Hannu Rämäkkö, Sofia Mäkikyrö, Lauri Koskinen

Proceedings of the 2020 IEEE Symposium in Low-Power and High-Speed Chips, 2020

2017

A 5.3 pJ/op approximate TTA VLIW tailored for machine learning.

Jukka Teittinen, Markus Hiienkari, Indre Zliobaite, Jaakko Hollmén, Heikki Berg, Juha Heiskala, Timo Viitanen, Jesse Simonsson, Lauri Koskinen

Microelectron. J., 2017

2015

Power optimizations for transport triggered SIMD processors.

Joonas Multanen, Timo Viitanen, Henry Linjamaki, Heikki Kultala, Pekka Jääskeläinen, Jarmo Takala, Lauri Koskinen, Jesse Simonsson, Heikki Berg, Kalle Raiskila, Tommi Zetterman

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015