Heikki Kultala

Orcid: 0000-0002-1845-2924

Affiliations:
  • Tampere University of Technology, Finland


According to our database1, Heikki Kultala authored at least 27 papers between 2008 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

Online presence:

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Bibliography

2020
Energy Efficient Low Latency Multi-issue Cores for Intelligent Always-On IoT Applications.
J. Signal Process. Syst., 2020

2019
LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio Coprocessor.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Blockwise Multi-Order Feature Regression for Real-Time Path-Tracing Reconstruction.
ACM Trans. Graph., 2019

Programmable and Scalable Architecture for Graphics Processing Units.
Trans. High Perform. Embed. Archit. Compil., 2019

Towards Efficient Code Generation for Exposed Datapath Architectures.
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, 2019

AEx: Automated Customization of Exposed Datapath Soft-Cores.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018
Variable Length Instruction Compression on Transport Triggered Architectures.
Int. J. Parallel Program., 2018

LoTTA: Energy-Efficient Processor for Always-On Applications.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

AivoTTA: an energy efficient programmable accelerator for CNN-based object recognition.
Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

Energy-Delay Trade-Offs in Instruction Register File Design.
Proceedings of the 2018 IEEE Nordic Circuits and Systems Conference, 2018

2017
MergeTree: A Fast Hardware HLBVH Constructor for Animated Ray Tracing.
ACM Trans. Graph., 2017

Exposed datapath optimizations for loop scheduling.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

2016
Improving Code Density with Variable Length Encoding Aware Instruction Scheduling.
J. Signal Process. Syst., 2016

Integer Linear Programming-Based Scheduling for Transport Triggered Architectures.
ACM Trans. Archit. Code Optim., 2016

Aggressively bypassing list scheduler for transport triggered architectures.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

OpenCL programmable exposed datapath high performance low-power image signal processor.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016

Customized high performance low power processor for binaural speaker localization.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
Code Density and Energy Efficiency of Exposed Datapath Architectures.
J. Signal Process. Syst., 2015

MergeTree: a HLBVH constructor for mobile systems.
Proceedings of the SIGGRAPH Asia 2015 Technical Briefs, Kobe, Japan, November 2-6, 2015, 2015

Power optimizations for transport triggered SIMD processors.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Programmable data parallel accelerator for mobile computer vision.
Proceedings of the 2015 IEEE Global Conference on Signal and Information Processing, 2015

2014
Compiler optimizations for code density of variable length instructions.
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014

A high throughput LDPC decoder using a mid-range GPU.
Proceedings of the IEEE International Conference on Acoustics, 2014

Heuristics for greedy transport triggered architecture interconnect exploration.
Proceedings of the 2014 International Conference on Compilers, 2014

2013
Turbo decoding on tailored OpenCL processor.
Proceedings of the 2013 9th International Wireless Communications and Mobile Computing Conference, 2013

2011
Operation set customization in retargetable compilers.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2008
Reducing Context Switch Overhead with Compiler-Assisted Threading.
Proceedings of the 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), 2008


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