Jian Li

Affiliations:
  • Futurewei Technologies Inc., Framingham, MA, USA
  • IBM Research, Austin, TX, USA (2006 - 2014)
  • Cornell University, Computer Systems Laboratory, Ithaca, NY, USA (PhD 2006)


According to our database1, Jian Li authored at least 26 papers between 2003 and 2022.

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Timeline

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Bibliography

2022
SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2022

2013
Scalable community detection in massive social networks using MapReduce.
IBM J. Res. Dev., 2013

Understanding system design for Big Data workloads.
IBM J. Res. Dev., 2013

Breaking the boundary for whole-system performance optimization of big data.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

2012
DuSCA: A multi-channeling strategy for doubling communication capacity in wireless NoC.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Transformer: a functional-driven cycle-accurate multicore simulator.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Proximity-Aware cache Replication.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Power-efficient time-sensitive mapping in heterogeneous systems.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
PERCS System Architecture.
Proceedings of the Encyclopedia of Parallel Computing, 2011

Design of multi-channel wireless NoC to improve on-chip communication capacity!
Proceedings of the NOCS 2011, 2011

Power shifting in Thrifty Interconnection Network.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

TAPO: Thermal-aware power optimization techniques for servers and data centers.
Proceedings of the 2011 International Green Computing Conference and Workshops, 2011

Scalable Proximity-Aware Cache Replication in Chip Multiprocessors.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Design exploration of hybrid caches with disparate memory technologies.
ACM Trans. Archit. Code Optim., 2010

A Framework for End-to-End Simulation of High-performance Computing Systems.
Simul., 2010

The PERCS High-Performance Interconnect.
Proceedings of the IEEE 18th Annual Symposium on High Performance Interconnects, 2010

Cost-driven 3D integration with interconnect layers.
Proceedings of the 47th Design Automation Conference, 2010

2009
Hybrid cache architecture with disparate memory technologies.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Thrifty interconnection network for HPC systems.
Proceedings of the 23rd international conference on Supercomputing, 2009

A novel architecture of the 3D stacked MRAM L2 cache for CMPs.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

Power and performance of read-write aware Hybrid Caches with non-volatile memories.
Proceedings of the Design, Automation and Test in Europe, 2009

2006
Dynamic power-performance adaptation of parallel computation on chip multiprocessors.
Proceedings of the 12th International Symposium on High-Performance Computer Architecture, 2006

2005
Power-performance considerations of parallel computing on chip multiprocessors.
ACM Trans. Archit. Code Optim., 2005

Power-Performance Implications of Thread-level Parallelism on Chip Multiprocessors.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005

2004
The Thrifty Barrier: Energy-Aware Synchronization in Shared-Memory Multiprocessors.
Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004

2003
RORIB: An Economic and Efficient Solution for Real-Time Online Remote Info Backup.
J. Database Manag., 2003


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