Danella Zhao

Affiliations:
  • Old Dominion University, Department of Computer Science, Norfolk, VA, USA
  • University of Louisiana at Lafayette, Center For Advanced Computer Studies, LA, USA


According to our database1, Danella Zhao authored at least 49 papers between 2002 and 2023.

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Bibliography

2023
μThingNet: Leveraging Fine-Grained Power Analysis towards A Robust Zero-Day Defender.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

SEEK: Detecting GPS Spoofing via a Sequential Dashcam-Based Vehicle Localization Framework.
Proceedings of the IEEE International Conference on Pervasive Computing and Communications, 2023

2022
Demo Abstract: A Distributed Power Side-channel Auditing System for Online loT Intrusion Detection.
Proceedings of the 21st ACM/IEEE International Conference on Information Processing in Sensor Networks, 2022

DeepAuditor: Distributed Online Intrusion Detection System for IoT Devices via Power Side-channel Auditing.
Proceedings of the 21st ACM/IEEE International Conference on Information Processing in Sensor Networks, 2022

ThingNet: A Lightweight Real-time Mirai IoT Variants Hunter through CPU Power Fingerprinting.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Energy-efficient task-resource co-allocation and heterogeneous multi-core NoC design in dark silicon era.
Microprocess. Microsystems, October, 2021

2018
Hotspot-aware task-resource co-allocation for heterogeneous many-core networks-on-chip.
Comput. Electr. Eng., 2018

Power- Thermal Aware Balanced Task-Resource Co-Allocation in Heterogeneous Many CPU-GPU Cores NoC in Dark Silicon Era.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

Neuro-NoC: Energy Optimization in Heterogeneous Many-Core NoC using Neural Networks in Dark Silicon Era.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
CAP-W: Congestion-aware platform for wireless-based network-on-chip in many-core era.
Microprocess. Microsystems, 2017

Optimizing the heterogeneous network on-chip design in manycore architectures.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Router-level performance driven dynamic management in hierarchical networks-on-chip.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Multi-objective Task Mapping Approach for Wireless NoC in Dark Silicon Age.
Proceedings of the 25th Euromicro International Conference on Parallel, 2017

Efficient Reconfigurable Global Network-on-Chip Designs towards Heterogeneous CPU-GPU Systems: An Application-Aware Approach.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Dark silicon-power-thermal aware runtime mapping and configuration in heterogeneous many-core NoC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Hierarchical approach for hybrid wireless Network-on-chip in many-core era.
Comput. Electr. Eng., 2016

Opening keynote: Crashing drones and hijacked cameras: Cybertrust meets cyberphysical.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Tutorial 2B: CMOS integrated system on a chip for neural interface applications.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

SAMi: Self-aware migration approach for congestion reduction in NoC-based MCSoC.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

ERFAN: Efficient reconfigurable fault-tolerant deflection routing algorithm for 3-D Network-on-Chip.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Plenary I: The Internet of important things.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

CATBR-Congestion Aware Traffic Bridging Routing among hierarchical networks-on-chip.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Efficient Congestion-Aware Scheme for Wireless on-Chip Networks.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

Task-Resource Co-Allocation for Hotspot Minimization in Heterogeneous Many-Core NoCs.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Shift sprinting: fine-grained temperature-aware NoC-based MCSoC architecture in dark silicon age.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
I(Re)2-WiNoC: Exploring scalable wireless on-chip micronetworks for heterogeneous embedded many-core SoCs.
Digit. Commun. Networks, 2015

Dynamic Application Mapping Algorithm for Wireless Network-on-Chip.
Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

2014
Message from program chairs.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

2012
Design of a scalable RF microarchitecture for heterogeneous MPSoCs.
Proceedings of the IEEE 25th International SOC Conference, 2012

DuSCA: A multi-channeling strategy for doubling communication capacity in wireless NoC.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011
Design of multi-channel wireless NoC to improve on-chip communication capacity!
Proceedings of the NOCS 2011, 2011

2010
A Low-Cost Deadlock-Free Design of Minimal-Table Rerouted XY-Routing for Irregular Wireless NoCs.
Proceedings of the NOCS 2010, 2010

2009
Distributed Flow Control and Buffer Management for Wireless Network-on-Chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
MTNet: Design of a Wireless Test Framework for Heterogeneous Nanometer Systems-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst., 2008

SD-MAC: Design and Synthesis of a Hardware-Efficient Collision-Free QoS-Aware MAC Protocol for Wireless Network-on-Chip.
IEEE Trans. Computers, 2008

Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints.
IEICE Trans. Inf. Syst., 2008

2007
Using Domain Partitioning in Wrapper Design for IP Cores Under Power Constraints.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Dual-channel binary-countdown medium access control in wireless network-on-chip.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

Design and Implementation of Routing Scheme for Wireless Network-on-Chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

The design and synthesis of a synchronous and distributed MAC protocol for wireless network-on-chip.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006
Design of a wireless test control network with radio-on-chip technology for nanometer system-on-a-chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

MTNET: Design and Optimization of a Wireless SOC Test Framework.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

2005
Dynamically partitioned test scheduling with adaptive TAM configuration for power-constrained SoC testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

A new SoC test architecture with RF/wireless connectivity.
Proceedings of the 10th European Test Symposium, 2005

2004
A generic resource distribution and test scheduling scheme for embedded core-based SoCs.
IEEE Trans. Instrum. Meas., 2004

2003
Power Constrained Test Scheduling with Dynamically Varied TAM.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Control Constrained Resource Partitioning for Complex SoCs.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002
Minimizing concurrent test time in SoC's by balancing resource usage.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002

Adaptive Test Scheduling in SoC's by Dynamic Partitioning.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002


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