Jiang Nan

Orcid: 0000-0002-8854-3055

According to our database1, Jiang Nan authored at least 9 papers between 2001 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2020
A Diode-Enhanced Scheme for Giant Magnetoresistance Amplification and Reconfigurable Logic.
IEEE Access, 2020

2019
Ultra-Dense Ring-Shaped Racetrack Memory Cache Design.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

2017
Compact modeling of high spin transfer torque efficiency double-barrier magnetic tunnel junction.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017

2016
Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

2008
A Session Key Generator Based on Chaotic Sequence.
Proceedings of the International Conference on Computer Science and Software Engineering, 2008

Relevant Feedback in Content-Based Engineering Drawing Retrieval.
Proceedings of the International Conference on Computer Science and Software Engineering, 2008

Color Design Scheme of Map for Color Vision Impaired.
Proceedings of the International Conference on Computer Science and Software Engineering, 2008

2001
Robust guaranteed cost control with H<sub>∞</sub>-γ disturbance attenuation performance.
Proceedings of the American Control Conference, 2001


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