Zhizhong Zhang
Affiliations:- Beihang University, School of Microelectronics, Fert Beijing Research Institute, Center for Big Data and Brain Computing (BDBC), Beijing, China
According to our database1,
Zhizhong Zhang authored at least 11 papers
between 2016 and 2025.
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Bibliography
2025
HRAMTran: A Hybrid-RAM Transformer Accelerator With Dynamic Sparsity Floating-Point CIM and Written-Back Transpose Array.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025
2021
Time-Domain Computing in Memory Using Spintronics for Energy-Efficient Convolutional Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2020
A Self-Matching Complementary-Reference Sensing Scheme for High-Speed and Reliable Toggle Spin Torque MRAM.
IEEE Trans. Circuits Syst., 2020
A Diode-Enhanced Scheme for Giant Magnetoresistance Amplification and Reconfigurable Logic.
IEEE Access, 2020
An In-memory Highly Reconfigurable Logic Circuit Based on Diode-assisted Enhanced Magnetoresistance Device.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019
2017
Compact modeling of high spin transfer torque efficiency double-barrier magnetic tunnel junction.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
2016
Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
Ultra-low power all spin logic device acceleration based on voltage controlled magnetic anisotropy.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016