Dafine Ravelosona

According to our database, Dafine Ravelosona authored at least 23 papers between 2011 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Forecasting the outcome of spintronic experiments with Neural Ordinary Differential Equations.

Xing Chen, Flavio Abreu Araujo, Mathieu Riou, Jacob Torrejon, Dafine Ravelosona, Wang Kang, Weisheng Zhao, Julie Grollier, Damien Querlioz

CoRR, 2021

2019

Ultra-Dense Ring-Shaped Racetrack Memory Cache Design.

Guanda Wang, Yue Zhang, Beibei Zhang, Bi Wu, Jiang Nan, Xueying Zhang, Zhizhong Zhang, Jacques-Olivier Klein, Dafine Ravelosona, Zhaohao Wang, Youguang Zhang, Weisheng Zhao

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2016

Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.

Yue Zhang, Chao Zhang, Jiang Nan, Zhizhong Zhang, Xueying Zhang, Jacques-Olivier Klein, Dafine Ravelosona, Guangyu Sun, Weisheng Zhao

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

2015

Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology.

Wang Kang, Yue Zhang, Zhaohao Wang, Jacques-Olivier Klein, Claude Chappert, Dafine Ravelosona, Gefei Wang, Youguang Zhang, Weisheng Zhao

ACM J. Emerg. Technol. Comput. Syst., 2015

Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM.

Wang Kang, Liuyang Zhang, Weisheng Zhao, Jacques-Olivier Klein, Youguang Zhang, Dafine Ravelosona, Claude Chappert

IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Perspectives of racetrack memory based on current-induced domain wall motion: From device to system.

Yue Zhang, Chao Zhang, Jacques-Olivier Klein, Dafine Ravelosona, Guangyu Sun, Weisheng Zhao

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

From device to system: cross-layer design exploration of racetrack memory.

Guangyu Sun, Chao Zhang, Hehe Li, Yue Zhang, Weiqi Zhang, Yizi Gu, Yinan Sun, Jacques-Olivier Klein, Dafine Ravelosona, Yongpan Liu, Weisheng Zhao, Huazhong Yang

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories.

Weisheng Zhao, Mathieu Moreau, Erya Deng, Yue Zhang, Jean-Michel Portal, Jacques-Olivier Klein, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller, Damien Querlioz, Nesrine Ben Romdhane, Dafine Ravelosona, Claude Chappert

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.

Weisheng Zhao, Jean-Michel Portal, Wang Kang, Mathieu Moreau, Yue Zhang, Hassen Aziza, Jacques-Olivier Klein, Zhaohao Wang, Damien Querlioz, Damien Deleruyelle, Marc Bocquet, Dafine Ravelosona, Christophe Muller, Claude Chappert

J. Parallel Distributed Comput., 2014

One-step majority-logic-decodable codes enable STT-MRAM for high speed working memories.

Wang Kang, Weisheng Zhao, Lun Yang, Jacques-Olivier Klein, Youguang Zhang, Dafine Ravelosona

Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014

Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires.

Nesrine Ben Romdhane, Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Z. R. Wang, Dafine Ravelosona

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Spintronics for low-power computing.

Yue Zhang, Weisheng Zhao, Jacques-Olivier Klein, Wang Kang, Damien Querlioz, Youguang Zhang, Dafine Ravelosona, Claude Chappert

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

An overview of spin-based integrated circuits.

Wang Kang, Weisheng Zhao, Zhaohao Wang, Jacques-Olivier Klein, Yue Zhang, Djaafar Chabi, Youguang Zhang, Dafine Ravelosona, Claude Chappert

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Magnetic Adder Based on Racetrack Memory.

Hong-Phuc Trinh, Weisheng Zhao, Jacques-Olivier Klein, Yue Zhang, Dafine Ravelosona, Claude Chappert

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

A low-cost built-in error correction circuit design for STT-MRAM reliability improvement.

Wang Kang, Weisheng Zhao, Zhaohao Wang, Yue Zhang, Jacques-Olivier Klein, Youguang Zhang, Claude Chappert, Dafine Ravelosona

Microelectron. Reliab., 2013

Spin-electronics based logic fabrics.

Weisheng Zhao, Jacques-Olivier Klein, Zhaohao Wang, Yue Zhang, Nesrine Ben Romdhane, Damien Querlioz, Dafine Ravelosona, Claude Chappert

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Emerging hybrid logic circuits based on non-volatile magnetic memories.

Weisheng Zhao, Guillaume Prenat, Jacques-Olivier Klein, Bernard Dieny, Claude Chappert, Dafine Ravelosona

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Synchronous full-adder based on complementary resistive switching memory cells.

Yue Zhang, Erya Deng, Jacques-Olivier Klein, Damien Querlioz, Dafine Ravelosona, Claude Chappert, Weisheng Zhao, Mathieu Moreau, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Analytical study of complementary memristive synchronous logic gates.

Jean-Michel Portal, Mathieu Moreau, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller, Yue Zhang, Erya Deng, Jacques-Olivier Klein, Damien Querlioz, Dafine Ravelosona, Claude Chappert, Weisheng Zhao

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

2012

Failure and reliability analysis of STT-MRAM.

Weisheng Zhao, Yue Zhang, Thibaut Devolder, Jacques-Olivier Klein, Dafine Ravelosona, Claude Chappert, Pascale Mazoyer

Microelectron. Reliab., 2012

Crossbar architecture based on 2R complementary resistive switching memory cell.

Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Damien Querlioz, Djaafar Chabi, Dafine Ravelosona, Claude Chappert, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

2011

High Performance SoC Design Using Magnetic Logic and Memory.

Weisheng Zhao, Lionel Torres, Luis Vitório Cargnini, Raphael Martins Brum, Yue Zhang, Yoann Guillemenet, Gilles Sassatelli, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, Dafine Ravelosona, Claude Chappert

Proceedings of the VLSI-SoC: Advanced Research for Systems on Chip, 2011

Design of MRAM based logic circuits and its applications.

Weisheng Zhao, Lionel Torres, Yoann Guillemenet, Luis Vitório Cargnini, Yahya Lakys, Jacques-Olivier Klein, Dafine Ravelosona, Gilles Sassatelli, Claude Chappert

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011