Shibin Tang

Orcid: 0000-0002-7560-2239

According to our database1, Shibin Tang authored at least 19 papers between 2010 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Mixed-granularity parallel coarse-grained reconfigurable architecture.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Flexible Rectification of a Speckle Projection System for Depth Sensing.
IEEE Trans. Instrum. Meas., 2021

Efficient Scheduling of Irregular Network Structures on CNN Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory.
IEEE Trans. Parallel Distributed Syst., 2019

A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications.
IEEE J. Solid State Circuits, 2018

Bit-width Adaptive Accelerator Design for Convolution Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns.
IEEE Trans. Very Large Scale Integr. Syst., 2017

AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

High-performance video content recognition with long-term recurrent convolutional network for FPGA.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

CRANarch: A feasible processor micro-architecture for Cloud Radio Access Network.
Microprocess. Microsystems, 2014

Microseismic Monitoring and Numerical Simulation of Rock Slope Failure.
Int. J. Distributed Sens. Networks, 2013

HRUL: A Hardware Assisted Recorder for User-Level Application.
Proceedings of the International Conference on Parallel and Distributed Computing, 2013

SimICT: A fast and flexible framework for performance and power evaluation of large-scale architecture.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Optimizing Web Browser on Many-Core Architectures.
Proceedings of the 12th International Conference on Parallel and Distributed Computing, 2011

Design Space Exploration of Parallel Architectures.
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011


GVE: Godson-T Verification Engine for many-core architecture rapid prototyping and debugging.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Thread Owned Block Cache: Managing Latency in Many-Core Architecture.
Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010