Shibin Tang

According to our database1, Shibin Tang authored at least 16 papers between 2010 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Parana: A Parallel Neural Architecture Considering Thermal Problem of 3D Stacked Memory.
IEEE Trans. Parallel Distrib. Syst., 2019

A High Throughput Acceleration for Hybrid Neural Networks With Efficient Resource Management on FPGA.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2019

2018
A High Energy Efficient Reconfigurable Hybrid Neural Network Processor for Deep Learning Applications.
J. Solid-State Circuits, 2018

Bit-width Adaptive Accelerator Design for Convolution Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Deep Convolutional Neural Network Architecture With Reconfigurable Computation Patterns.
IEEE Trans. VLSI Syst., 2017

AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs.
Proceedings of the IEEE 6th Non-Volatile Memory Systems and Applications Symposium, 2017

High-performance video content recognition with long-term recurrent convolutional network for FPGA.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2014
CRANarch: A feasible processor micro-architecture for Cloud Radio Access Network.
Microprocess. Microsystems, 2014

2013
Microseismic Monitoring and Numerical Simulation of Rock Slope Failure.
IJDSN, 2013

HRUL: A Hardware Assisted Recorder for User-Level Application.
Proceedings of the International Conference on Parallel and Distributed Computing, 2013

SimICT: A fast and flexible framework for performance and power evaluation of large-scale architecture.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

2011
Optimizing Web Browser on Many-Core Architectures.
Proceedings of the 12th International Conference on Parallel and Distributed Computing, 2011

Design Space Exploration of Parallel Architectures.
Proceedings of the Multi-objective Design Space Exploration of Multiprocessor SoC Architectures, 2011

2010

GVE: Godson-T Verification Engine for many-core architecture rapid prototyping and debugging.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Thread Owned Block Cache: Managing Latency in Many-Core Architecture.
Proceedings of the Euro-Par 2010 - Parallel Processing, 16th International Euro-Par Conference, Ischia, Italy, August 31, 2010


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