Jiann-Chyi Rau

According to our database, Jiann-Chyi Rau authored at least 26 papers between 1998 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

A Scan-Based Lower-Power Testing Architecture for Modern Circuits.

Jiann-Chyi Rau, Jia-Xiang Wang

Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2021

2013

Compact Test Pattern Selection for Small Delay Defect.

Chia-Yuan Chang, Kuan-Yu Liao, Sheng-Chang Hsu, James Chien-Mo Li, Jiann-Chyi Rau

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

2012

Optimal unknown bit filtering for test response masking.

Ding-ke Weng, Jiann-Chyi Rau, Cheng-Han Lin

Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012

2011

Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment.

Jiann-Chyi Rau, Po-Han Wu

IET Comput. Digit. Tech., 2011

2010

The AB-filling methodology for power-aware at-speed scan testing.

Tsung-Tang Chen, Po-Han Wu, Kung-Han Chen, Jiann-Chyi Rau, Shih-Ming Tzeng

Proceedings of the 2011 IEEE International Test Conference, 2010

Multi-chains encoding scheme in low-cost ATE.

Gong-Han Chen, Po-Han Wu, Jiann-Chyi Rau

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Multi-cycle compress technique for high-speed IP in low-cost environment.

Gong-Han Chen, Chu-Chuan Lin, Po-Han Wu, Jiann-Chyi Rau

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009

Low power multi-chains encoding scheme for SoC in low-cost environment.

Po-Han Wu, Jiann-Chyi Rau

Proceedings of the 2009 IEEE International Test Conference, 2009

Reducing Switching Activity by Test Slice Difference Technique for Test Volume Compression.

Wei-Lin Li, Po-Han Wu, Jiann-Chyi Rau

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

New Scheme of Reducing Shift and Capture Power Using the X-Filling Methodology.

Tsung-Tang Chen, Wei-Lin Li, Po-Han Wu, Jiann-Chyi Rau

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

The grid-based two-layer routing algorithm suitable for cell/IP-based circuit design.

Chia-Jung Liu, Yi-Chen Lin, Jiann-Chyi Rau

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Test slice difference technique for low power encoding.

Wei-Lin Li, Tsung-Tang Chen, Po-Han Wu, Jiann-Chyi Rau

Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

An efficient test-data compaction for low power VLSI testing.

Po-Han Wu, Tsung-Tang Chen, Wei-Lin Li, Jiann-Chyi Rau

Proceedings of the 2008 IEEE International Conference on Electro/Information Technology, 2008

2006

A broadcast-based test scheme for reducing test size and application time.

Jiann-Chyi Rau, Jun-Yi Chang, Chien-Shiun Chen

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Novel Hardware Architecture for Low Power and Rapid Testing of VLSI Circuits.

Jiann-Chyi Rau, Po-Han Wu, Chia-Jung Liu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Design of Dynamically Assignmentable TAM Width for Testing Core-Based SOCs.

Jiann-Chyi Rau, Chien-Shiun Chen, Po-Han Wu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

A novel reseeding mechanism for pseudo-random testing of VLSI circuits.

Jiann-Chyi Rau, Ying-Fu Ho, Po-Han Wu

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Reconfigurable multiple scan-chains for reducing test application time of SOCs.

Jiann-Chyi Rau, Chih-Lung Chien, Jia-Shing Ma

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains.

Jiann-Chyi Rau, Ching-Hsiu Lin, Jun-Yi Chang

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

An Enhanced Tree-Structured Scan Chain for Pseudo-Exhaustive Testing of VLSI Circuits.

Jiann-Chyi Rau, Kuo-Chun Kuo

Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

An Efficient Mechanism for Debugging RTL Description.

Jiann-Chyi Rau, Yi-Yuan Chang, Chia-Hung Lin

Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

2002

A don't-care based image circuit for function verification.

Jiann-Chyi Rau, Yan-Min Chen, Shih-Chieh Chang

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001

A timing-driven pseudoexhaustive testing for VLSI circuits.

Shih-Chieh Chang, Jiann-Chyi Rau

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

2000

A compact factored form for a Boolean function.

Jiann-Chyi Rau, Yan-Min Chen, Shih-Chieh Chang

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A timing-driven pseudo-exhaustive testing of VLSI circuits.

Shih-Chieh Chang, Jiann-Chyi Rau

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1998

A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits.

Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998