Shih-Chieh Chang
Orcid: 0000-0003-0717-6466
According to our database1,
Shih-Chieh Chang
authored at least 161 papers
between 1992 and 2024.
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Bibliography
2024
8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2024
A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips.
IEEE J. Solid State Circuits, January, 2024
2023
IEEE Trans. Circuits Syst. II Express Briefs, December, 2023
A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips.
IEEE J. Solid State Circuits, March, 2023
U-MRAM: Transistor-Less, High-Speed (10 ns), Low-Voltage (0.6 V), Field-Free Unipolar MRAM for High-Density Data Memory.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
Proceedings of the 2023 International Symposium on Physical Design, 2023
Gait Analysis in Powered Exoskeleton-Assisted Walking in Patients with Stroke: A Case Series Cohort.
Proceedings of the Asia Pacific Signal and Information Processing Association Annual Summit and Conference, 2023
2022
A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
CoRR, 2020
15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
AirConcierge: Generating Task-Oriented Dialogue via Efficient Large-Scale Knowledge Retrieval.
Proceedings of the Findings of the Association for Computational Linguistics: EMNLP 2020, 2020
Proceedings of the Computer Vision - ECCV 2020 Workshops, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2020
2019
Hierarchical LSTM: Modeling Temporal Dynamics and Taxonomy in Location-Based Mobile Check-Ins.
Proceedings of the Advances in Knowledge Discovery and Data Mining, 2019
Proceedings of the 7th International Conference on Learning Representations, 2019
Proceedings of the 2019 IEEE/CVF International Conference on Computer Vision, 2019
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
CoRR, 2018
Proceedings of the International Conference on Computer-Aided Design, 2018
2017
Perfect Hashing Based Parallel Algorithms for Multiple String Matching on Graphic Processing Units.
IEEE Trans. Parallel Distributed Syst., 2017
Leak Stopper: An Actively Revitalized Snoop Filter Architecture with Effective Generation Control.
ACM Trans. Design Autom. Electr. Syst., 2017
Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Proceedings of the Machine Learning and Knowledge Discovery in Databases, 2017
A Dynamic Deep Neural Network Design for Efficient Workload Allocation in Edge Computing.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviation.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
RECORD: Temporarily Randomized Encoding of COmbinational Logic for Resistance to Data Leakage from hardware Trojan.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016
A novel low-cost dynamic logic reconfigurable structure strategy for low power optimization.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016
2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
Soft-Error-Tolerant Design Methodology for Balancing Performance, Power, and Reliability.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
Frequency of Low Clouds in Taiwan Retrieved from MODIS Data and Its Relation to Cloud Forest Occurrence.
Remote. Sens., 2015
A Novel Application of Multiscale Entropy in Electroencephalography to Predict the Efficacy of Acetylcholinesterase Inhibitor in Alzheimer's Disease.
Comput. Math. Methods Medicine, 2015
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015
Hybrid coverage assertions for efficient coverage analysis across simulation and emulation environments.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Multibit Retention Registers for Power Gated Designs: Concept, Design, and Deployment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
Critical Path Monitor Enabled Dynamic Voltage Scaling for Graceful Degradation in Sub-Threshold Designs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
IEEE Trans. Computers, 2013
Strengthening Modern Electronics Industry Through the National Program for Intelligent Electronics in Taiwan.
IEEE Access, 2013
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
ACM Trans. Design Autom. Electr. Syst., 2012
Efficient Wakeup Scheduling Considering Both Resource Usage and Timing Budget for Power Gating Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012
Efficient on-line module-level wake-up scheduling for high performance multi-module designs.
Proceedings of the International Symposium on Physical Design, 2012
Memory-efficient pattern matching architectures using perfect hashing on graphic processing units.
Proceedings of the IEEE INFOCOM 2012, Orlando, FL, USA, March 25-30, 2012, 2012
Efficient multiple-bit retention register assignment for power gated design: Concept and algorithms.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
A probabilistic analysis method for functional qualification under Mutation Analysis.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Proceedings of the International SoC Design Conference, 2011
Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
On the preconditioner of conjugate gradient method - A power grid simulation perspective.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011
Accelerating Regular Expression Matching Using Hierarchical Parallel Machines on GPU.
Proceedings of the Global Communications Conference, 2011
Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
An Efficient Wake-Up Strategy Considering Spurious Glitches Phenomenon for Power Gating Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2010
Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Sleep Transistor Sizing for Leakage Power Minimization Considering Temporal Correlation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
Acute Response <i>in vivo</i> of a Fiber-Optic Sensor for Continuous Glucose Monitoring from Canine Studies on Point Accuracy.
Sensors, 2010
Synthesis of an efficient controlling structure for post-silicon clock skew minimization.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the Global Communications Conference, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
An efficient phase detector connection structure for the skew synchronization system.
Proceedings of the 47th Design Automation Conference, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Efficient Boolean Characteristic Function for Timed Automatic Test Pattern Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
2008
ACM Trans. Design Autom. Electr. Syst., 2008
Proceedings of the 26th International Conference on Computer Design, 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Efficient Transition-Mode Boolean Characteristic Function with Its Application to Maximum Instantaneous Current Analysis.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Analysis and optimization of power-gated ICs with multiple power gating configurations.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the 44th Design Automation Conference, 2007
Proceedings of the 44th Design Automation Conference, 2007
Proceedings of the 2007 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
ACM Trans. Design Autom. Electr. Syst., 2006
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006
Proceedings of the 43rd Design Automation Conference, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
2003
Embedded core test generation using broadcast test architecture and netlist scrambling.
IEEE Trans. Reliab., 2003
2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
2001
VLSI Design, 2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001
2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000
1999
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999
Proceedings of the 36th Conference on Design Automation, 1999
1998
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
Proceedings of the 35th Conference on Design Automation, 1998
1997
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997
1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996
Proceedings of the 1996 European Design and Test Conference, 1996
1995
Proceedings of the 32st Conference on Design Automation, 1995
Proceedings of the 32st Conference on Design Automation, 1995
1994
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994
Proceedings of the 31st Conference on Design Automation, 1994
1992
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992