Shih-Chieh Chang

According to our database1, Shih-Chieh Chang authored at least 147 papers between 1992 and 2020.

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Bibliography

2020
Contextual Temperature for Language Modeling.
CoRR, 2020

Calibrated BatchNorm: Improving Robustness Against Noisy Weights in Neural Networks.
CoRR, 2020

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

AirConcierge: Generating Task-Oriented Dialogue via Efficient Large-Scale Knowledge Retrieval.
Proceedings of the 2020 Conference on Empirical Methods in Natural Language Processing: Findings, 2020

Remix: Rebalanced Mixup.
Proceedings of the Computer Vision - ECCV 2020 Workshops, 2020

Accuracy Tolerant Neural Networks Under Aggressive Power Optimization.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Person Identification by Walking Gesture Using Skeleton Sequences.
Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2020

2019
Learning with Hierarchical Complement Objective.
CoRR, 2019

Hierarchical LSTM: Modeling Temporal Dynamics and Taxonomy in Location-Based Mobile Check-Ins.
Proceedings of the Advances in Knowledge Discovery and Data Mining, 2019

Complement Objective Training.
Proceedings of the 7th International Conference on Learning Representations, 2019

Improving Adversarial Robustness via Guided Complement Entropy.
Proceedings of the 2019 IEEE/CVF International Conference on Computer Vision, 2019

Aging-aware chip health prediction adopting an innovative monitoring strategy.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
An Adaptive Mechanism for Designing Efficient Snoop Filters.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Contactless Testing for Prebond Interposers.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Sensor-Based Time Speculation in the Presence of Timing Variability.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

MONAS: Multi-Objective Neural Architecture Search using Reinforcement Learning.
CoRR, 2018

Searching toward pareto-optimal device-aware neural architectures.
Proceedings of the International Conference on Computer-Aided Design, 2018

2017
Editorial.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Perfect Hashing Based Parallel Algorithms for Multiple String Matching on Graphic Processing Units.
IEEE Trans. Parallel Distributed Syst., 2017

Leak Stopper: An Actively Revitalized Snoop Filter Architecture with Effective Generation Control.
ACM Trans. Design Autom. Electr. Syst., 2017

Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

DC-Prophet: Predicting Catastrophic Machine Failures in DataCenters.
Proceedings of the Machine Learning and Knowledge Discovery in Databases, 2017

A Dynamic Deep Neural Network Design for Efficient Workload Allocation in Edge Computing.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

CN-SIM: A cycle-accurate full system power delivery noise simulator.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2016

High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Overoptimistic voltage scaling in pre-error AVS systems and learning-based alleviation.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

RECORD: Temporarily Randomized Encoding of COmbinational Logic for Resistance to Data Leakage from hardware Trojan.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

A novel low-cost dynamic logic reconfigurable structure strategy for low power optimization.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015
A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Soft-Error-Tolerant Design Methodology for Balancing Performance, Power, and Reliability.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Frequency of Low Clouds in Taiwan Retrieved from MODIS Data and Its Relation to Cloud Forest Occurrence.
Remote. Sens., 2015

A Novel Application of Multiscale Entropy in Electroencephalography to Predict the Efficacy of Acetylcholinesterase Inhibitor in Alzheimer's Disease.
Comput. Math. Methods Medicine, 2015

Q-Learning Based Dynamic Voltage Scaling for Designs with Graceful Degradation.
Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Hybrid coverage assertions for efficient coverage analysis across simulation and emulation environments.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Thermal-Aware On-Line Scheduler for 3-D Many-Core Processor Throughput Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

A Fuzzy-Matching Model With Grid Reduction for Lithography Hotspot Detection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Multibit Retention Registers for Power Gated Designs: Concept, Design, and Deployment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

Concurrency-oriented SoC re-certification by reusing block-level test vectors.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Package geometric aware thermal analysis by infrared-radiation thermal images.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Contactless Stacked-die Testing for Pre-bond Interposers.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Critical Path Monitor Enabled Dynamic Voltage Scaling for Graceful Degradation in Sub-Threshold Designs.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Embedding Repeaters in Silicon IPs for Cross-IP Interconnections.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Accelerating Pattern Matching Using a Novel Parallel Algorithm on GPUs.
IEEE Trans. Computers, 2013

Strengthening Modern Electronics Industry Through the National Program for Intelligent Electronics in Taiwan.
IEEE Access, 2013

On the futility of thermal through-silicon-vias.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Low-power timing closure methodology for ultra-low voltage designs.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

A novel fuzzy matching model for lithography hotspot detection.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic.
ACM Trans. Design Autom. Electr. Syst., 2012

Efficient Wakeup Scheduling Considering Both Resource Usage and Timing Budget for Power Gating Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Efficient on-line module-level wake-up scheduling for high performance multi-module designs.
Proceedings of the International Symposium on Physical Design, 2012

Memory-efficient pattern matching architectures using perfect hashing on graphic processing units.
Proceedings of the IEEE INFOCOM 2012, Orlando, FL, USA, March 25-30, 2012, 2012

Efficient multiple-bit retention register assignment for power gated design: Concept and algorithms.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Mitigating lifetime underestimation: A system-level approach considering temperature variations and correlations between failure mechanisms.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

A probabilistic analysis method for functional qualification under Mutation Analysis.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Post silicon skew tuning: Survey and analysis.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Performance Optimization Using Variable-Latency Design Style.
IEEE Trans. Very Large Scale Integr. Syst., 2011

Efficient Pattern Matching Algorithm for Memory Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2011

TSV fault-tolerant mechanisms with application to 3D clock networks.
Proceedings of the International SoC Design Conference, 2011

Analysis and mitigation of NBTI-induced performance degradation for power-gated circuits.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

A robust architecture for post-silicon skew tuning.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Useful-skew clock optimization for multi-power mode designs.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

On the preconditioner of conjugate gradient method - A power grid simulation perspective.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Accelerating Regular Expression Matching Using Hierarchical Parallel Machines on GPU.
Proceedings of the Global Communications Conference, 2011

Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization.
Proceedings of the Design, Automation and Test in Europe, 2011

Fault-tolerant 3D clock network.
Proceedings of the 48th Design Automation Conference, 2011

NBTI-aware power gating design.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
An Efficient Wake-Up Strategy Considering Spurious Glitches Phenomenon for Power Gating Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Sleep Transistor Sizing for Leakage Power Minimization Considering Temporal Correlation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Acute Response <i>in vivo</i> of a Fiber-Optic Sensor for Continuous Glucose Monitoring from Canine Studies on Point Accuracy.
Sensors, 2010

Synthesis of an efficient controlling structure for post-silicon clock skew minimization.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Accelerating String Matching Using Multi-Threaded Algorithm on GPU.
Proceedings of the Global Communications Conference, 2010

Clock skew optimization considering complicated power modes.
Proceedings of the Design, Automation and Test in Europe, 2010

An efficient phase detector connection structure for the skew synchronization system.
Proceedings of the 47th Design Automation Conference, 2010

2009
Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Spare Cells With Constant Insertion for Engineering Change.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Efficient Boolean Characteristic Function for Timed Automatic Test Pattern Generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008
Synthesis of a novel timing-error detection architecture.
ACM Trans. Design Autom. Electr. Syst., 2008

Timing analysis considering IR drop waveforms in power gating designs.
Proceedings of the 26th International Conference on Computer Design, 2008

A novel sequential circuit optimization with clock gating logic.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Optimization of Pattern Matching Circuits for Regular Expression on FPGA.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Intelligent Random Vector Generator Based on Probability Analysis of Circuit Structure.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Efficient Transition-Mode Boolean Characteristic Function with Its Application to Maximum Instantaneous Current Analysis.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Electromigration and voltage drop aware power grid optimization for power gated ICs.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007

Analysis and optimization of power-gated ICs with multiple power gating configurations.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Engineering change using spare cells with constant insertion.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

An Efficient Mechanism for Performance Optimization of Variable-Latency Designs.
Proceedings of the 44th Design Automation Conference, 2007

Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization.
Proceedings of the 44th Design Automation Conference, 2007

Optimization of pattern matching algorithm for memory based architecture.
Proceedings of the 2007 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2007

2006
Power minimization for dynamic PLAs.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Multiple wire reconnections based on implication flow graph.
ACM Trans. Design Autom. Electr. Syst., 2006

Language-Based High Level Transaction Extraction on On-chip Buses.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Efficient Boolean characteristic function for fast timed ATPG.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Optimization of regular expression pattern matching circuits on FPGA.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

Timing driven power gating.
Proceedings of the 43rd Design Automation Conference, 2006

Delay variation tolerance for domino circuits.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
FPGA technology mapping optimization by rewiring algorithms.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Design and design automation of rectification logic for engineering change.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Power estimation starategies for a low-power security processor.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
A vectorless estimation of maximum instantaneous current for sequential circuits.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Re-synthesis for delay variation tolerance.
Proceedings of the 41th Design Automation Conference, 2004

Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
Embedded core test generation using broadcast test architecture and netlist scrambling.
IEEE Trans. Reliab., 2003

2002
Crosstalk alleviation for dynamic PLAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

A don't-care based image circuit for function verification.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Random Pattern Testability Enhancement by Circuit Rewiring.
VLSI Design, 2001

Theorems and extensions of single wire replacement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

A timing-driven pseudoexhaustive testing for VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Charge-sharing alleviation and detection for CMOS domino circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Embedded Core Testing Using Broadcast Test Architecture.
Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000
TAIR: testability analysis by implication reasoning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

A compact factored form for a Boolean function.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A timing-driven pseudo-exhaustive testing of VLSI circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Wire Reconnections Based on Implication Flow Graph.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits.
Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

Novel techniques for improving testability analysis.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

Charge sharing fault analysis and testing for CMOS domino logic circuits.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
Efficient Boolean division and substitution using redundancy addition and removing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Circuit Optimization by Rewiring.
IEEE Trans. Computers, 1999

Power reduction through iterative gate sizing and voltage scaling.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Synthesis for multiple input wires replacement of a gate for wiring consideration.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Charge Sharing Fault Detection for CMOS Domino Logic Circuits.
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications.
Proceedings of the 36th Conference on Design Automation, 1999

1998
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

A novel combinational testability analysis by considering signal correlation.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Efficient Boolean Division and Substitution.
Proceedings of the 35th Conference on Design Automation, 1998

1997
Postlayout logic restructuring using alternative wires.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

1996
Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Perturb and simplify: multilevel Boolean network optimizer.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Fast Boolean optimization by rewiring.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Perturb and Simplify: Optimizing Combinational Circuits with External Don't Cares.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Logic Synthesis for Engineering Change.
Proceedings of the 32st Conference on Design Automation, 1995

An Efficient Algorithm for Local Don't Care Sets Calculation.
Proceedings of the 32st Conference on Design Automation, 1995

1994
Perturb and simplify: multi-level boolean network optimizer.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Minimizing ROBDD Size of Incompletely Specified Multiple Output Functions.
Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Layout Driven Logic Synthesis for FPGAs.
Proceedings of the 31st Conference on Design Automation, 1994

1992
Technology Mapping via Transformations of Function Graphs.
Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992


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