Jin Guo

Affiliations:
  • IMEC, Leuven, Belgium


According to our database1, Jin Guo authored at least 5 papers between 2006 and 2008.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2008
A tool flow for predicting system level timing failures due to interconnect reliability degradation.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007
Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Topology exploration for energy efficient intra-tile communication.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Physical design implementation of segmented buses to reduce communication energy.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006


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