Kris Croes

According to our database1, Kris Croes authored at least 58 papers between 1989 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Degradation mechanisms and lifetime assessment of Ge Vertical PIN photodetectors.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2022

System-Level Simulation of Electromigration in a 3 nm CMOS Power Delivery Network: The Effect of Grid Redundancy, Metallization Stack and Standard-Cell Currents.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

Degradation mechanisms in Germanium Electro-Absorption Modulators.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

Assessment of critical Co electromigration parameters.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

Reliability Investigation of W2W Hybrid Bonding Interface: Breakdown Voltage and Leakage Mechanism.
Proceedings of the IEEE International Reliability Physics Symposium, 2022

2021
A Novel System-Level Physics-Based Electromigration Modelling Framework: Application to the Power Delivery Network.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2021

Electromigration limits of copper nano-interconnects.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

Reliability of Mo as Word Line Metal in 3D NAND.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

Reliability of a DME Ru Semidamascene scheme with 16 nm wide Airgaps.
Proceedings of the IEEE International Reliability Physics Symposium, 2021

Novel low thermal budget gate stack solutions for BTI reliability in future Logic Device technologies : Invited paper.
Proceedings of the International Conference on IC Design and Technology, 2021

2020
Electrical and Optical Reliability Analysis of GeSi Electro-Absorption Modulators.
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020

Conduction and Breakdown Mechanisms in Low-k Spacer and Nitride Spacer Dielectric Stacks in Middle of Line Interconnects.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Metal reliability mechanisms in Ruthenium interconnects.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Dielectric Reliability Study of 21 nm Pitch Interconnects with Barrierless Ru Fill.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019
Role of Defects in the Reliability of HfO2/Si-Based Spacer Dielectric Stacks for Local Interconnects.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Accelerated Device Degradation of High-Speed Ge Waveguide Photodetectors.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

New Access to Soft Breakdown Parameters of Low-k Dielectrics Through Localisation-Based Analysis.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Understanding EM-Degradation Mechanisms in Metal Heaters Used for Si Photonics Applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Low-Frequency Noise Measurements to Characterize Cu-Electromigration Down to 44nm Metal Pitch.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

2018
SOT-MRAM 300mm integration for low power and ultrafast embedded memories.
CoRR, 2018

SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded Memories.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018


Insights into metal drift induced failure in MOL and BEOL.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

TSV process-induced MOS reliability degradation.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Method to assess the impact of LER and spacing variation on BEOL dielectric reliability using 2D-field simulations for <20nm spacing.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

Stress mitigation of 3D-stacking/packaging induced stresses.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

The first observation of p-type electromigration failure in full ruthenium interconnects.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2017
LER and spacing variability on BEOL TDDB using E-field mapping: Impact of field acceleration.
Microelectron. Reliab., 2017

Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects.
Microelectron. Reliab., 2017

Lock-in thermal laser stimulation for non-destructive failure localization in 3-D devices.
Microelectron. Reliab., 2017

2016
Design considerations for the mechanical integrity of airgaps in nano-interconnects under chip-package interaction; a numerical investigation.
Microelectron. Reliab., 2016

Evaluation of via density and low-k Young's modulus influence on mechanical performance of advanced node multi-level Back-End-Of-Line.
Microelectron. Reliab., 2016

Reliability Challenges Related to TSV Integration and 3-D Stacking.
IEEE Des. Test, 2016

2015
Microstructure simulation of grain growth in Cu through silicon vias using phase-field modeling.
Microelectron. Reliab., 2015

Constant voltage electromigration for advanced BEOL copper interconnects.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Impact of oxide liner properties on TSV Cu pumping and TSV stress.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Intrinsic reliability of local interconnects for N7 and beyond.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

Impact of process variability on BEOL TDDB lifetime model assessment.
Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014
As-grown donor-like traps in low-k dielectrics and their impact on intrinsic TDDB reliability.
Microelectron. Reliab., 2014

Reliability challenges for barrier/liner system in high aspect ratio through silicon vias.
Microelectron. Reliab., 2014


2013
TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Diffusion growth of Cu<sub>3</sub>Sn phase in the bump and thin film Cu/Sn structures.
Microelectron. Reliab., 2012

2011
Cu pumping in TSVs: Effect of pre-CMP thermal budget.
Microelectron. Reliab., 2011

Influence of test structure design on stress-induced-voiding using an experimentally validated Finite Element Modeling approach.
Microelectron. Reliab., 2011

2009
Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
Study of copper drift during TDDB of intermetal dielectrics by using fully passivated MOS capacitors as test vehicle.
Microelectron. Reliab., 2008

A tool flow for predicting system level timing failures due to interconnect reliability degradation.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2006
Hardware and a Tool Chain for ADRES.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2002
High-resolution SILC measurements of thin SiO<sub>2</sub> at ultra low voltages.
Microelectron. Reliab., 2002

Statistical aspects of the degradation of LDD nMOSFETs.
Microelectron. Reliab., 2002

2001
A new degradation model and lifetime extrapolation technique for lightly doped drain nMOSFETs under hot-carrier degradation.
Microelectron. Reliab., 2001

High-resolution in-situ of gold electromigration: test time reduction.
Microelectron. Reliab., 2001

1999
Matisse: A System-on-Chip Design Methodology Emphasizing Dynamic Memory Management.
J. VLSI Signal Process., 1999

1998
Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer.
Proceedings of the 35th Conference on Design Automation, 1998

1989
REDUSA: module generation by automatic elimination of superfluous blocks in regular structures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989


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