Antonis Papanikolaou

According to our database1, Antonis Papanikolaou authored at least 38 papers between 2002 and 2018.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2018
Optimized Consumer-Centric Demand Response.
Proceedings of the 2018 Global Internet of Things Summit, 2018

2015
Demonstrating HW-SW Transient Error Mitigation on the Single-Chip Cloud Computer Data Plane.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Classification Framework for Analysis and Modeling of Physically Induced Reliability Violations.
ACM Comput. Surv., 2015

Open system for energy services (OS4ES): An EU-funded research project to establish a non-discriminatory, multivendor-capability service delivery platform for smart grid services.
Proceedings of the 2015 IEEE International Conference on Smart Grid Communications, 2015

Combined Visual Comfort and Energy Efficiency through True Personalization of Automated Lighting Control.
Proceedings of the SMARTGREENS 2015, 2015

2013
Enabling Efficient System Configurations for Dynamic Wireless Applications Using System Scenarios.
Int. J. Wirel. Inf. Networks, 2013

Accelerating All-to-All Protein Structures Comparison with TMalign Using a NoC Many-Cores Processor Architecture.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systems.
Proceedings of the Design, Automation and Test in Europe, 2013

2011
Enabling efficient system configurations for dynamic wireless baseband engines using system scenarios.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

CAD tools for designing 3D integrated systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Power, performance and area prediction of 3D ICs during early stage design exploration in 45nm.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010
Control for Power Gating of Wires.
IEEE Trans. Very Large Scale Integr. Syst., 2010

A Temperature-Aware Time-Dependent Dielectric Breakdown Analysis Framework.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

BIT-width exploration over 3D architectures using high-level synthesis.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Fast Design Space Exploration Environment Applied on NoC's for 3D-Stacked MPSoC's.
Proceedings of the ARCS '10, 2010

2009
3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot.
Proc. IEEE, 2009

System-level process variability compensation on memory organizations: on the scalability of multi-mode memories.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Combining system scenarios and configurable memories to tolerate unpredictability.
ACM Trans. Design Autom. Electr. Syst., 2008

A tool flow for predicting system level timing failures due to interconnect reliability degradation.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007
Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Using a Linear Sectioned Bus And a Communication Processor to Reduce Energy Costs in Synchronous On-Chip Communication.
Proceedings of the International Symposium on System-on-Chip, 2007

Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

At Tape-out: Can System Yield in Terms of Timing/Energy Specifications Be Predicted?
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Topology exploration for energy efficient intra-tile communication.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Reliability Issues in Deep Deep Submicron Technologies: Time-Dependent Variability and its Impact on Embedded System Design.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

System-level process variability compensation on memory organizations of dynamic applications: a case study.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Yield prediction for architecture exploration in nanometer technology nodes: : a model and case study for memory organizations.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Physical design implementation of segmented buses to reduce communication energy.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005
Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Architectural and Physical Design Optimizations for Efficient Intra-tile Communication.
Proceedings of the 2005 International Symposium on System-on-Chip, 2005

A system-level methodology for fully compensating process variability impact of memory organizations in periodic applications.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

2004
Overcoming the "Memory Wall" by improved system design exploration and a link to process technology options.
Proceedings of the First Conference on Computing Frontiers, 2004

A global bus power optimization methodology for physical design of memory dominated systems by coupling bus segmentation and activity driven block placement.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Global interconnect trade-off for technology over memory modules to application level: case study.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

2002
Interconnect exploration for future wire dominated technologies.
Proceedings of the Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), 2002


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