Michele Stucchi

According to our database1, Michele Stucchi authored at least 31 papers between 2002 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2022

Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
Localization of Electrical Defects in Hybrid Bonding Interconnect Structures by Scanning Photocapacitance Microscopy.
IEEE Trans. Instrum. Meas., 2021

2020
Metal reliability mechanisms in Ruthenium interconnects.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Accurate Measurements of Small Resistances in Vertical Interconnects with Small Aspect Ratios.
Proceedings of the IEEE European Test Symposium, 2020

2019
Understanding EM-Degradation Mechanisms in Metal Heaters Used for Si Photonics Applications.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

2018
Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits.
Proceedings of the IEEE International Test Conference, 2018

TSV process-induced MOS reliability degradation.
Proceedings of the IEEE International Reliability Physics Symposium, 2018

2017
Lock-in thermal laser stimulation for non-destructive failure localization in 3-D devices.
Microelectron. Reliab., 2017

2016
Reliability Challenges Related to TSV Integration and 3-D Stacking.
IEEE Des. Test, 2016

Continuity and reliability assessment of a scalable 3×50μm and 2×40μm via-middle TSV module.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
Impact of interconnect multiple-patterning variability on SRAMs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Reliability challenges for barrier/liner system in high aspect ratio through silicon vias.
Microelectron. Reliab., 2014

2012
Capacitance Measurements of Two-Dimensional and Three-Dimensional IC Interconnect Structures by Quasi-Static C-V Technique.
IEEE Trans. Instrum. Meas., 2012

2011
Fine grain thermal modeling and experimental validation of 3D-ICs.
Microelectron. J., 2011

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology.
IEEE J. Solid State Circuits, 2011

2010

3D integration: Circuit design, test, and reliability challenges.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot.
Proc. IEEE, 2009

Impact of 3D design choices on manufacturing cost.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV).
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
A tool flow for predicting system level timing failures due to interconnect reliability degradation.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2006
Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies.
IEEE J. Solid State Circuits, 2006

Impact of interconnect resistance increase on system performance of low power and high performance designs.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Statistically Aware SRAM Memory Array Design.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2004
Interconnect width selection for deep submicron designs using the table lookup method.
Proceedings of the Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), 2004

2003
Global interconnect trade-off for technology over memory modules to application level: case study.
Proceedings of the 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), 2003

2002
Frequency dependence in interline capacitance measurements.
IEEE Trans. Instrum. Meas., 2002

Interconnect exploration for future wire dominated technologies.
Proceedings of the Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), 2002

Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate.
Proceedings of the 2002 Design, 2002


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