Paul Marchal

According to our database1, Paul Marchal authored at least 48 papers between 2000 and 2013.

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Bibliography

2013
Design issues in heterogeneous 3D/2.5D integration.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
A calibrated pathfinding model for signal integrity analysis on interposer.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
Fine grain thermal modeling and experimental validation of 3D-ICs.
Microelectron. J., 2011

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology.
IEEE J. Solid State Circuits, 2011

Editorial- three-dimensional integrated circuits design.
IET Comput. Digit. Tech., 2011

3D heterogeneous system integration: application driver for 3D technology development.
Proceedings of the 48th Design Automation Conference, 2011

DRAM-on-logic Stack - Calibrated thermal and mechanical models integrated into PathFinding flow.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Analysis of microbump induced stress effects in 3D stacked IC technologies.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

In-tier diagnosis of power domains in 3D TSV ICs.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010

3D NoCs - Unifying inter & intra chip communication.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

3D integration: Circuit design, test, and reliability challenges.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

An RDL-configurable 3D memory tier to replace on-chip SRAM.
Proceedings of the Design, Automation and Test in Europe, 2010

3-D stacked die: now or future?
Proceedings of the 47th Design Automation Conference, 2010

Verifying electrical/thermal/thermo-mechanical behavior of a 3D stack - Challenges and solutions.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
3-D Technology Assessment: Path-Finding the Technology/Design Sweet-Spot.
Proc. IEEE, 2009

Pathfinding: A design methodology for fast exploration and optimisation of 3D-stacked integrated circuits.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

A novel DRAM architecture as a low leakage alternative for SRAM caches in a 3D interconnect context.
Proceedings of the Design, Automation and Test in Europe, 2009

System-level power/performance evaluation of 3D stacked DRAMs for mobile applications.
Proceedings of the Design, Automation and Test in Europe, 2009

Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

Evaluation of energy-recovering interconnects for low-power 3D stacked ICs.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

HOT TOPIC - 3D Integration or How to Scale in the 21st Century.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support.
IEEE Trans. Computers, 2007

Exploring temperature-aware design in low-power MPSoCs.
Int. J. Embed. Syst., 2007

Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

At Tape-out: Can System Yield in Terms of Timing/Energy Specifications Be Predicted?
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Exploration of Low Power Adders for a SIMD Data Path.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Reliability issues in deep deep sub-micron technologies: time-dependent variability and its impact on embedded system design.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture.
Proceedings of the Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), 2006

Physical design implementation of segmented buses to reduce communication energy.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Data-Access Optimization of Embedded Systems Through Selective Inlining Transformation.
Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, 2005

Flexible Hardware/Software Support for Message Passing on a Distributed Shared Memory Architecture.
Proceedings of the 2005 Design, 2005

Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

2004
Integrated Task Scheduling and Data Assignment for SDRAMs in Dynamic Applications.
IEEE Des. Test Comput., 2004

An integrated hardware/software approach for run-time scratchpad management.
Proceedings of the 41th Design Automation Conference, 2004

Optimizing the memory bandwidth with loop fusion.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Optimizing the Memory Bandwidth with Loop Morphing.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2003
SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms.
Proceedings of the 2003 Design, 2003

SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms.
Proceedings of the Embedded Software for SoC, 2003

2002
Matador: An Exploration Environment for System-Design.
J. Circuits Syst. Comput., 2002

Managing Dynamic Concurrent Tasks in Embedded Real-Time Multimedia Systems.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

2001
Energy-Aware Runtime Scheduling for Embedded-Multiprocessor SOCs.
IEEE Des. Test Comput., 2001

Optimisation Problems for Dynamic Concurrent Task-Based Systems.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Task concurrency management methodology summary.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Task concurrency management methodology to schedule the MPEG4 IM1 player on a highly parallel processor platform.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

2000
Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform.
Proceedings of the Power-Aware Computer Systems, First International Workshop, 2000

Task Concurrency Management Experiment for Power-Efficient Speed-up of Embedded MPEG4 IM1 Player.
Proceedings of the 2000 International Workshop on Parallel Processing, 2000


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